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Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--

Keiji KISHINE, Noboru ISHIHARA, Haruhiko ICHINO

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Summary :

This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.

Publication
IEICE TRANSACTIONS on Electronics Vol.E84-C No.4 pp.460-469
Publication Date
2001/04/01
Publicized
Online ISSN
DOI
Type of Manuscript
PAPER
Category
Integrated Electronics

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