This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.

We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.

We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply.

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.

A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.

In this paper, we present a 10 Gbase Ethernet Transceiver that is suitable for 10 Gb/s Ethernet applications. The 10 Gbase Ethernet Transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18 µm SOI/CMOS process and dissipates 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of the advance CMOS process, this 10 GbE transceiver realizes a low power, low cost and compact solution for the exponentially increasing need of broadband network applications.

This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.

This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.