IEICE TRANSACTIONS on Communications
82.5GS/s (8×10.3GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation
Summary :
We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E101-B No.4 pp.987-994
- Publication Date
- 2018/04/01
- Publicized
- 2017/10/18
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.2017OAP0001
- Type of Manuscript
- Special Section PAPER (Special Section on Optical Access System for Social Life)
- Category
Authors
Naoki SUZUKI
Mitsubishi Electric Corporation
Kenichi NAKURA
Mitsubishi Electric Corporation
Takeshi SUEHIRO
Mitsubishi Electric Corporation
Seiji KOZAKI
Mitsubishi Electric Corporation
Junichi NAKAGAWA
Mitsubishi Electric Corporation
Kuniaki MOTOSHIMA
Mitsubishi Electric Corporation
Keyword
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Naoki SUZUKI, Kenichi NAKURA, Takeshi SUEHIRO, Seiji KOZAKI, Junichi NAKAGAWA, Kuniaki MOTOSHIMA, "82.5GS/s (8×10.3GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation" in IEICE TRANSACTIONS on Communications,
vol. E101-B, no. 4, pp. 987-994, April 2018, doi: 10.1587/transcom.2017OAP0001.
Abstract: We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2017OAP0001/_p
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@ARTICLE{e101-b_4_987,
author={Naoki SUZUKI, Kenichi NAKURA, Takeshi SUEHIRO, Seiji KOZAKI, Junichi NAKAGAWA, Kuniaki MOTOSHIMA, },
journal={IEICE TRANSACTIONS on Communications},
title={82.5GS/s (8×10.3GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation},
year={2018},
volume={E101-B},
number={4},
pages={987-994},
abstract={We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.},
keywords={},
doi={10.1587/transcom.2017OAP0001},
ISSN={1745-1345},
month={April},}
Copy
TY - JOUR
TI - 82.5GS/s (8×10.3GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation
T2 - IEICE TRANSACTIONS on Communications
SP - 987
EP - 994
AU - Naoki SUZUKI
AU - Kenichi NAKURA
AU - Takeshi SUEHIRO
AU - Seiji KOZAKI
AU - Junichi NAKAGAWA
AU - Kuniaki MOTOSHIMA
PY - 2018
DO - 10.1587/transcom.2017OAP0001
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E101-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2018
AB - We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.
ER -
English
