We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

In this paper, a novel method of resource abstraction and an abstracted-resource model for dynamic resource control in optical access networks are proposed. Based on this proposal, an implementation assuming application to 5G mobile fronthaul and backhaul is presented. Finally, an evaluation of the processing time for resource allocation using this method is performed using a software prototype of the control function. From the results of the evaluation, it is confirmed that the proposed method offers better characteristics than former approaches, and is suitable for dynamic resource control in 5G applications.

PON (Passive Optical Network) achieves FTTH (Fiber To The Home) economically, by sharing an optical fiber among plural subscribers. Recently, global climate change has been recognized as a serious near term problem. Power saving techniques for electronic devices are important. In PON system, the ONU (Optical Network Unit) power saving scheme has been studied and defined in XG-PON. In this paper, we propose an ONU power saving scheme for EPON. Then, we present an analysis of the power reduction effect and the data transmission delay caused by the ONU power saving scheme. According to the analysis, we propose an efficient provisioning method for the ONU power saving scheme which is applicable to both of XG-PON and EPON.

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.