PON (Passive Optical Network) achieves FTTH (Fiber To The Home) economically, by sharing an optical fiber among plural subscribers. Recently, global climate change has been recognized as a serious near term problem. Power saving techniques for electronic devices are important. In PON system, the ONU (Optical Network Unit) power saving scheme has been studied and defined in XG-PON. In this paper, we propose an ONU power saving scheme for EPON. Then, we present an analysis of the power reduction effect and the data transmission delay caused by the ONU power saving scheme. According to the analysis, we propose an efficient provisioning method for the ONU power saving scheme which is applicable to both of XG-PON and EPON.

A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.

A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.