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Kazuomi KUBOTA Yoichi MAEDA Kazuyuki AIHARA
Nonlinear dynamics of xn+1=λ {4xn (1-xn)}q is studied in this paper. Different from the logistic map (q=1), in the case of q
Kenji NAKANISHI Akihiro OTAKA Yoichi MAEDA
This paper describes international standardization activities on B-PON, GE-PON, and G-PON. This paper explains their distinctive technologies, and compares them from the technical view. This paper also mentions future PON standards which are discussed in some standardization bodies.
Masayuki TANIMOTO Kohichi SAKANIWA Kiyoharu AIZAWA Kazuyoshi OSHIMA Kiyomi KUMOZAKI Shuji TASAKA Yoichi MAEDA Takeshi MIZUIKE Mikio YAMASHITA Hideaki YAMANAKA Koichiro WAKASUGI Masaaki KATAYAMA
Hanan T. Al-AWADHI Tomoki AONO Senling WANG Yoshinobu HIGAMI Hiroshi TAKAHASHI Hiroyuki IWATA Yoichi MAEDA Jun MATSUSHIMA
Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.
Youichi FUKADA Takeshi YASUDA Shuji KOMATSU Koichi SAITO Yoichi MAEDA Yasuyuki OKUMURA
This paper describes a novel adaptive clock recovery method that uses proportional-integral-derivative (PID) control. The adaptive clock method is a clock recovery technique that synchronizes connected terminals via packet networks, and will be indispensable for circuit emulation services in the next generation Ethernet. Our adaptive clock method simultaneously achieves a short starting-time, accuracy, stable recovery clock frequency, and few buffer delays using the PID control technique. We explain the numerical simulations, experimental results, and circuit designs.
Tomoya HATANO Jun-ichi KANI Yoichi MAEDA
This paper reviews access system standardization activities and related technologies from the viewpoints of optical-based PON access, mobile access systems including LPWAN, and access network virtualization. Future study issues for the next access systems are also presented.