We recorded time series data of calls of Japanese tree frogs (Hyla japonica; Nihon-Ama-Gaeru) and examined the dynamics of the experimentally observed data not only through linear time series analysis such as power spectra but also through nonlinear time series analysis such as reconstruction of orbits with delay coordinates and different kinds of recurrence plots, namely the conventional recurrence plot (RP), the iso-directional recurrence plot (IDRP), and the iso-directional neighbors plot (IDNP). The results show that a single frog called nearly periodically, and a pair of frogs called nearly periodically but alternately in almost anti-phase synchronization with little overlap through mutual interaction. The fundamental frequency of the calls of a single frog during the interactive calling between two frogs was smaller than when the same frog first called alone. We also used the recurrence plots to study nonlinear and nonstationary determinism in the transition of the calling behavior. Moreover, we quantified the determinism of the nonlinear and nonstationary dynamics with indices of the ratio R of the number of points in IDNP to that in RP and the percentage PD of contiguous points forming diagonal lines in RP by the recurrence quantification analysis (RQA). Finally, we discuss a possibility of mathematical modeling of the calling behavior and a possible biological meaning of the call alternation.

We analyze additive effects of nonlinear dynamics for conbinatorial optimization. We apply chaotic time series as noise sequence to neural networks for 10-city and 20-city traveling salesman problems and compare the performance with stochastic processes, such as Gaussian random numbers, uniform random numbers, 1/fα noise and surrogate data sets which preserve several statistics of the original chaotic data. In result, it is shown that not only chaotic noise but also surrogates with similar autocorrelation as chaotic noise exhibit high solving abilities. It is also suggested that since temporal structure of chaotic noise characterized by autocorrelation affects abilities for combinatorial optimization problems, effects of chaotic sequence as additive noise for escaping from undesirable local minima in case of solving combinatorial optimization problems can be replaced by stochastic noise with similar autocorrelation.

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.

In this paper, we propose a new strategy of estimating correlation dimensions in combination with the method of surrogate data, which is a kind of statistical control usually introduced to avoid spurious estimates of nonlinear statistics, such as fractal dimensions, Lyapunov exponents and so on. In the case of analyzing time series with the method of surrogate data, it is desirable to decide values of estimated nonlinear statistics of the original data and surrogate data sets as exactly as possible. However, when dimensional analysis is applied to possible attractors reconstructed from real time series, it is very dangerous to decide a single value as the estimated dimensions and desirable to analyze its scaling property for avoiding spurious estimates. In order to solve this defficulty, a dimension estimator algorithm and the method of surrogate data are combined by introducing Monte Carlo hypothesis testing. In order to show effectiveness of the new strategy, firstly artificial time series are analyzed, such as the Henon map with additive noise, filtered random numbers and filtered random numbers transformed by a static monotonic nonlinearity, and then experimental time series are also examined, such as wolfer's sunspot numbers and the fluctuations in a farinfrared laser data.

In this paper, we propose algorithm of deterministic nonlinear prediction, or a modified version of the method of analogues which was originally proposed by E.N. Lorenz (J. Atom. Sci., 26, 636-646, 1969), and apply it to the artificial time series data produced from nonlinear dynamical systems and further corrupted by superimposed observational noise. The prediction performance of the present method are investigated by calculating correlation coefficients, root mean square errors and signature errors and compared with the prediction algorithm of local linear approximation method. As a result, it is shown that the prediction performance of the proposed method are better than those of the local linear approximation especially in case that the amount of noise is large.

We propose a novel method for analysis of time-related neuronal activities. This method can be used for the detection of firing patterns in the presence of noise, which is inevitable in physiological experiments. This method is also useful for probability density estimation, because it enables precise information quantification from a small amount of data.

In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

A fuzzy-like phenomenon is observed in a chaotic neural network operating as dynamic autoassociative memory. When an external stimulation with properties shared by two stored patterns is applied to the chaotic neural network, the output of the network transits between the two patterns. The ratio of the network visiting two stored patterns is dependent on the ratio of the Hamming distances between the external stimulation and the two stored patterns. This phenomenon is similar to the human decision-making process, which can be described by fuzzy set theory. Here, we analyze the fuzzy-like phenomenon from the viewpoint of the fuzzy set theory.

Electroencephalographic (EEG) potentials are analysed by the Lyapunov spectrum in order to evaluate the orbital instability peculiar to deterministic chaos quantitatively. First, the Lyapunov spectra are estimated to confirm the existence of chaotic behavior in EEG data by the optimal approximation of Jacobian matrix in the reconstructed statespace. Second, the same method is applied to a neural network model with chaotic dynamics, the macroscopic average activity of which is analysed as a simple model of EEG data. The first analysis shows that the largest Lyapunov exponent is actually positive in the EEG data. On the other hand, the second analysis on the chaotic neural network shows that the positive largest Lyapunov exponent can be obtained by observing only the macroscopic average activity. Thus, these results indicate the possibility that one can know the existence of chaotic dynamics in the brain by analysing the Lyapunov spectrum of the macroscopic EEG data.

The hippocampus is thought to play an important role in the transformation from short-term memory into long-term memory, which is called consolidation. The physiological phenomenon of synaptic change called LTP or LTD has been studied as a basic mechanism for learning and memory. The neural network mechanism of the consolidation, however, is not clarified yet. The authors' approach is to construct information processing theory in learning and memory, which can explain the physiological data and behavioral data. This paper proposes a dynamical hippocampal model which can store and recall spatial input patterns. The authors assume that the primary functions of hippocampus are to store episodic information of sensory signals and to keep them for a while until the neocortex stores them as a long-term memory. On the basis of the hippocampal architecture and hypothetical synaptic dynamics of LTP/LTD, the authors construct a hippocampal model. This model considers: (1) divergent connections, (2) the synaptic dynamics of LTP and LTD based on pre- and postsynaptic coincidence, and (3) propagation of LTD. Computer simulations show that this model can store and recall its input spatial pattern by self-organizing closed activating pathways. By the backward propagation of LTD, the synaptic pathway for a specific spatial input pattern can be selected among the divergent closed connections. In addition, the output pattern also suggests that this model is sensitive to the temporal timing of input signals. This timing sensitivity suggests the applicability to spatio-temporal input patterns of this model. Future extensions of this model are also discussed.

A model of a single neuron with chaotic dynamics is implemented with current-mode circuit design technique. The existence of chaotic dynamics in the circuit is demonstrated by simulation with SPICE3. The proposed circuit is suitable for implementing a chaotic neural network composed of such neuron models on a VLSI chip.

A fuzzy-like phenomenon in a dynamic neural network is demonstrated and analyzed. The network operates as a dynamic associative memory. Each neuron of the dynamic neural network has an all-or-none output and exponentially decaying refractoriness. When several related patterns are stored in the dynamic neural network and an external stimulus with a property shared by two of the stored patterns is applied to the neural network, the output of the neural network dynamically transits between the two stored patterns. The frequency ratio that the network visits the two stored patterns is dependent on the ratio of the Hamming distances between the external pattern and the two stored patterns. This phenomenon is similar to the human decision-making process, some of which characteristics can be described by fuzzy set theory. A framework for the analysis of this phenomenon is proposed, and is used to derive sufficient conditions which ensure the dynamical transition between the two stored patterns. The properties of the transition in the network are also discussed.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.

This paper proposes a new chaos generator circuit with a current sampling scheme. This circuit generates an arbitrary nonlinear function corresponding to the time-domain current waveform supplied from an external source by using a pulse phase modulation approach. The measurement results of a fabricated chip with TSMC 0.25 µm process technology demonstrate that the proposed circuit can generate chaos signals even if D/A conversion is used for nonlinear waveform generation, because a current integral by sampling with a short pulse smooths the quantized nonlinear function.

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-to-analog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 60.44dB, even with an op-amp with a poor DC gain (< 50dB) while dissipating 780µW in analog circuits at 1.4V and occupying an active area of 0.25 × 0.26mm2.

Nonlinear dynamics of xn+1=λ {4xn (1-xn)}q is studied in this paper. Different from the logistic map (q=1), in the case of q

A 12-bit 1.25MS/s cyclic analog-to-digital converter (ADC) is designed and fabricated in 90nm CMOS technology, and only occupies an active area as small as 0.037mm2. The proposed ADC is composed of a non-binary AD convertion stage, and a on-chip non-binary-to-binary digital block includes a built-in radix-value self-estimation scheme. Therefore, althouh a non-binary convertion architechture is adopted, the proposed ADC is the same as other stand-alone binary ADCs. The redundancy of non-binary 1-bit/step architecture relaxes the accuracy requirement on analog components of ADC. As a result, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density Metal-Oxide-Metal (MOM) capacitors can be used to achieve a small chip area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 62.3dB using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The proposed ADC dissipated 490µW in analog circuits at 1.4V power supply and 1.25Msps (20MHz clocking). The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz sinusoidal input.

A family of nonlinear resistor circuits with Λ and V-type I-V characteristics is proposed by using capacitively coupled multi-input MOSFETs. Their I-V characteristics can be easily altered by external control voltages. Moreover, the proposed circuits are fully compatible with a standard CMOS semiconductor process because only enhancement-type MOSFETs are necessary. Furthermore, nonlinear capacitors can be used for the capacitively coupled multi-input MOSFETs in the proposed circuits, so that a simple digital CMOS process with nonlinear capacitors can be used to fabricate the proposed circuits. Simple equations for a numerical simulation of the circuits are derived. Moreover, results from numerical simulations and experiments with discrete elements are demonstrated.

Based on the similarity between the neural and the immune networks, a modified PDP model is adopted to simulate the idiotype networks of the immune system. Major modifications peculiar to immune networks are the introduction of time delays and the bilateral and asymmetric interaction between units. Simulation results show nonlinear behaviors of networks such as hard oscillations and chaos. The behaviors are closely related to the structure of networks. It is suggested that the analysis of the immune system can inspire new scheme in parallel distributed information processing.