In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

A fuzzy-like phenomenon is observed in a chaotic neural network operating as dynamic autoassociative memory. When an external stimulation with properties shared by two stored patterns is applied to the chaotic neural network, the output of the network transits between the two patterns. The ratio of the network visiting two stored patterns is dependent on the ratio of the Hamming distances between the external stimulation and the two stored patterns. This phenomenon is similar to the human decision-making process, which can be described by fuzzy set theory. Here, we analyze the fuzzy-like phenomenon from the viewpoint of the fuzzy set theory.

Electroencephalographic (EEG) potentials are analysed by the Lyapunov spectrum in order to evaluate the orbital instability peculiar to deterministic chaos quantitatively. First, the Lyapunov spectra are estimated to confirm the existence of chaotic behavior in EEG data by the optimal approximation of Jacobian matrix in the reconstructed statespace. Second, the same method is applied to a neural network model with chaotic dynamics, the macroscopic average activity of which is analysed as a simple model of EEG data. The first analysis shows that the largest Lyapunov exponent is actually positive in the EEG data. On the other hand, the second analysis on the chaotic neural network shows that the positive largest Lyapunov exponent can be obtained by observing only the macroscopic average activity. Thus, these results indicate the possibility that one can know the existence of chaotic dynamics in the brain by analysing the Lyapunov spectrum of the macroscopic EEG data.

The hippocampus is thought to play an important role in the transformation from short-term memory into long-term memory, which is called consolidation. The physiological phenomenon of synaptic change called LTP or LTD has been studied as a basic mechanism for learning and memory. The neural network mechanism of the consolidation, however, is not clarified yet. The authors' approach is to construct information processing theory in learning and memory, which can explain the physiological data and behavioral data. This paper proposes a dynamical hippocampal model which can store and recall spatial input patterns. The authors assume that the primary functions of hippocampus are to store episodic information of sensory signals and to keep them for a while until the neocortex stores them as a long-term memory. On the basis of the hippocampal architecture and hypothetical synaptic dynamics of LTP/LTD, the authors construct a hippocampal model. This model considers: (1) divergent connections, (2) the synaptic dynamics of LTP and LTD based on pre- and postsynaptic coincidence, and (3) propagation of LTD. Computer simulations show that this model can store and recall its input spatial pattern by self-organizing closed activating pathways. By the backward propagation of LTD, the synaptic pathway for a specific spatial input pattern can be selected among the divergent closed connections. In addition, the output pattern also suggests that this model is sensitive to the temporal timing of input signals. This timing sensitivity suggests the applicability to spatio-temporal input patterns of this model. Future extensions of this model are also discussed.

A model of a single neuron with chaotic dynamics is implemented with current-mode circuit design technique. The existence of chaotic dynamics in the circuit is demonstrated by simulation with SPICE3. The proposed circuit is suitable for implementing a chaotic neural network composed of such neuron models on a VLSI chip.

A fuzzy-like phenomenon in a dynamic neural network is demonstrated and analyzed. The network operates as a dynamic associative memory. Each neuron of the dynamic neural network has an all-or-none output and exponentially decaying refractoriness. When several related patterns are stored in the dynamic neural network and an external stimulus with a property shared by two of the stored patterns is applied to the neural network, the output of the neural network dynamically transits between the two stored patterns. The frequency ratio that the network visits the two stored patterns is dependent on the ratio of the Hamming distances between the external pattern and the two stored patterns. This phenomenon is similar to the human decision-making process, some of which characteristics can be described by fuzzy set theory. A framework for the analysis of this phenomenon is proposed, and is used to derive sufficient conditions which ensure the dynamical transition between the two stored patterns. The properties of the transition in the network are also discussed.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.

This paper proposes a new chaos generator circuit with a current sampling scheme. This circuit generates an arbitrary nonlinear function corresponding to the time-domain current waveform supplied from an external source by using a pulse phase modulation approach. The measurement results of a fabricated chip with TSMC 0.25 µm process technology demonstrate that the proposed circuit can generate chaos signals even if D/A conversion is used for nonlinear waveform generation, because a current integral by sampling with a short pulse smooths the quantized nonlinear function.

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-to-analog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 60.44dB, even with an op-amp with a poor DC gain (< 50dB) while dissipating 780µW in analog circuits at 1.4V and occupying an active area of 0.25 × 0.26mm2.

Nonlinear dynamics of xn+1=λ {4xn (1-xn)}q is studied in this paper. Different from the logistic map (q=1), in the case of q

A 12-bit 1.25MS/s cyclic analog-to-digital converter (ADC) is designed and fabricated in 90nm CMOS technology, and only occupies an active area as small as 0.037mm2. The proposed ADC is composed of a non-binary AD convertion stage, and a on-chip non-binary-to-binary digital block includes a built-in radix-value self-estimation scheme. Therefore, althouh a non-binary convertion architechture is adopted, the proposed ADC is the same as other stand-alone binary ADCs. The redundancy of non-binary 1-bit/step architecture relaxes the accuracy requirement on analog components of ADC. As a result, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density Metal-Oxide-Metal (MOM) capacitors can be used to achieve a small chip area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 62.3dB using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The proposed ADC dissipated 490µW in analog circuits at 1.4V power supply and 1.25Msps (20MHz clocking). The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz sinusoidal input.

A family of nonlinear resistor circuits with Λ and V-type I-V characteristics is proposed by using capacitively coupled multi-input MOSFETs. Their I-V characteristics can be easily altered by external control voltages. Moreover, the proposed circuits are fully compatible with a standard CMOS semiconductor process because only enhancement-type MOSFETs are necessary. Furthermore, nonlinear capacitors can be used for the capacitively coupled multi-input MOSFETs in the proposed circuits, so that a simple digital CMOS process with nonlinear capacitors can be used to fabricate the proposed circuits. Simple equations for a numerical simulation of the circuits are derived. Moreover, results from numerical simulations and experiments with discrete elements are demonstrated.

Based on the similarity between the neural and the immune networks, a modified PDP model is adopted to simulate the idiotype networks of the immune system. Major modifications peculiar to immune networks are the introduction of time delays and the bilateral and asymmetric interaction between units. Simulation results show nonlinear behaviors of networks such as hard oscillations and chaos. The behaviors are closely related to the structure of networks. It is suggested that the analysis of the immune system can inspire new scheme in parallel distributed information processing.

In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.

An asynchronous pulse neural network model which is suitable for VLSI implementation is proposed. The model neuron can function as a coincidence detector as well as an integrator depending on its internal time-constant relative to the external one, and show complex dynamical behavior including chaotic responses. A network with the proposed neurons can process spatio-temporal coded information through dynamical cell assemblies with functional synaptic connections.

Deterministic nonlinear prediction is applied to both artificial and real time series data in order to investigate orbital-instabilities, short-term predictabilities and long-term unpredictabilities, which are important characteristics of deterministic chaos. As an example of artificial data, bimodal maps of chaotic neuron models are approximated by radial basis function networks, and the approximation abilities are evaluated by applying deterministic nonlinear prediction, estimating Lyapunov exponents and reconstructing bifurcation diagrams of chaotic neuron models. The functional approximation is also applied to squid giant axon response as an example of real data. Two metnods, the standard and smoothing interpolation, are adopted to construct radial basis function networks; while the former is the conventional method that reproduces data points strictly, the latter considers both faithfulness and smoothness of interpolation which is suitable under existence of noise. In order to take a balance between faithfulness and smoothness of interpolation, cross validation is applied to obtain an optimal one. As a result, it is confirmed that by the smoothing interpolation prediction performances are very high and estimated Lyapunov exponents are very similar to actual ones, even though in the case of periodic responses. Moreover, it is confirmed that reconstructed bifurcation diagrams are very similar to the original ones.

We propose a novel segmentation algorithm which combines an image segmentation method into small regions with chaotic neurodynamics that has already been clarified to be effective for solving some combinatorial optimization problems. The basic algorithm of an image segmentation is the variable-shape-bloch-segmentation (VB) which searches an opti-mal state of the segmentation by moving the vertices of quadran-gular regions. However, since the algorithm for moving vertices is based upon steepest descent dynamics, this segmentation method has a local minimum problem that the algorithm gets stuck at undesirable local minima. In order to treat such a problem of the VB and improve its performance, we introduce chaotic neurodynamics for optimization. The results of our novel method are compared with those of conventional stochastic dynamics for escaping from undesirable local minima. As a result, the better results are obtained with the chaotic neurodynamical image segmentation.

We analyse a mathematical neuron model with chaotic dynamics, or a chaotic neuron model by the generalized dimensions and the f(α) spectrum. The results show that the multi-fractal structure of a chaotic neuron model can be quantified by the f(α) spectrum.

This paper presents an improved current-mode circuit for implementation of a chaotic neuron model. The proposed circuit uses a switched-current integrator and a nonlinear output function circuit, which is based on an operational transconductance amplifier, as building blocks. Is is shown by SPICE simulations and experiments using discrete elements that the proposed circuit well replicates the behavior of the chaotic neuron model.

Though response of neurons is mainly decided by synaptic events, the length of a time window for the neuronal response has still not been clarified. In this paper, we analyse the time window within which a neuron processes synaptic events, on the basis of the Hodgkin-Huxley equations. Our simulation shows that an active membrane property makes neurons' behavior complex, and that a few milliseconds is plausible as the time window. A neuron seems to detect coincidence synaptic events in such a time window.