A model of a single neuron with chaotic dynamics is implemented with current-mode circuit design technique. The existence of chaotic dynamics in the circuit is demonstrated by simulation with SPICE3. The proposed circuit is suitable for implementing a chaotic neural network composed of such neuron models on a VLSI chip.

Switched-capacitor chaotic neurons fabricated in a full-custom integrated circuit are used to investigate the behavior of 2- and 3-neuron chaotic neural networks. Various sets of parameters are used to visualize the dynamical responses of the networks. Hysteresis of the network is also demonstrated. Lyapunov exponents are approximated from the measured data to characterize the state of each neuron. The effect of the finite length of data and the rounding effect of data acquisition system to the computation of Lyapunov exponents are briefly discussed.

A family of nonlinear resistor circuits with Λ and V-type I-V characteristics is proposed by using capacitively coupled multi-input MOSFETs. Their I-V characteristics can be easily altered by external control voltages. Moreover, the proposed circuits are fully compatible with a standard CMOS semiconductor process because only enhancement-type MOSFETs are necessary. Furthermore, nonlinear capacitors can be used for the capacitively coupled multi-input MOSFETs in the proposed circuits, so that a simple digital CMOS process with nonlinear capacitors can be used to fabricate the proposed circuits. Simple equations for a numerical simulation of the circuits are derived. Moreover, results from numerical simulations and experiments with discrete elements are demonstrated.

An asynchronous pulse neural network model which is suitable for VLSI implementation is proposed. The model neuron can function as a coincidence detector as well as an integrator depending on its internal time-constant relative to the external one, and show complex dynamical behavior including chaotic responses. A network with the proposed neurons can process spatio-temporal coded information through dynamical cell assemblies with functional synaptic connections.

This paper presents an improved current-mode circuit for implementation of a chaotic neuron model. The proposed circuit uses a switched-current integrator and a nonlinear output function circuit, which is based on an operational transconductance amplifier, as building blocks. Is is shown by SPICE simulations and experiments using discrete elements that the proposed circuit well replicates the behavior of the chaotic neuron model.

Switched-Capacitor (SC) low-pass ladder filters based on the LDI transformation, have been successfully designed using the Lossless Discrete Integrators (LDIs) as their basic building blocks. However, the design of highpass ladder filters with the LDIs are not straightforward as the low-pass or bandpass case. On the other hand, a high-pass design is achieved easily by using a differentiator as the building block, instead of an integrator. Thus, a new design technique of Switched-Capacitor Modified Lossless Discrete Differentiators (MLDDs) is proposed in this paper. By using them as the basic building block, SC high-pass ladder filters are directly constructed based on the low-pass to high-pass transformation. Furthermore, a fully-differential architecture is applied to this MLDD design, and some MLDD alternatives are investigated for high-frequency and time-sharing applications.

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

One of the motives of recent studies for designing discrete-time impedances by using the Switched-Capacitor (SC) technology, is to simulate general impedances such as FDNR, Super-L and so on. Authors have previously proposed the Switched-Capacitor Impedance Simulation Circuit (SC-ISC)" to accomplish this purpose. In this paper, an improved version of the SC-ISC, which is based on the LDI sz transformation, is proposed, with the partly-differential structure. One of the advantages of using the partly-differential structure is that exact LDI immittances are easily obtained. Furthemore, a Lossless Discrete Differentiator is simply simulated with a LDI integrator by using the enhanced flexibility of the differential form. Furthermore, by applying the improved SC-ISC, a design technique of a new Frequency Dependent Voltage Controlled Current Source Pir (FD-VCCS-P)" is proposed. In this respect, two kinds of special FD-VCCS-Ps are investigated. Moreover, their simple applications are described, and the results of experiments and simulations are also reported.

Recently, many non-traditional applications of Switched-Capacitor circuits have been popularly studied. As one of those applications, we present here a new constructing technique of a Switched-Capacitor Impedance Simulation Circuit (SC-ISC) with unity-gain buffers. Any desired impedance can be obtained by applying this SC-ISC technique. To make up a SC-ISC simply and generally, four kinds of basic constructing Units and two types of feedback circuits are introduced. Furthermore, by applying those Units, an arbitrary transfer function can be easily synthesized. In addition, some algorithms to obtain useful impedances are proposed. Several SC-ISC impedances were experimentally constructed and theoretically analyzed. In particular, some kinds of simple filters and oscillators were made and tested. They were also theoretically analyzed.