A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.

In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

First, a number of issues pertaining to analog VLSI implementation of Backpropagation (BP) and Deterministic Boltzmann Machine (DBM) learning algorithms are clarified. According to the results from software simulation, a mismatch between the activation function and derivative generated by independent circuits degrades the BP learning performance. The perfomance can be improved, however, by adjusting the gain of the activation function used to obtain the derivative, irrespective of the original activation function. Calculation errors embedded in the circuits also degrade the learning preformance. BP learning is sensitive to offset errors in multiplication in the learning process, and DBM learning is sensitive to asymmetry between the weight increment and decrement processes. Next, an analog VLSI architecture for implementing the algorithms using common building block circuits is proposed. The evaluation results of test chips confirm that synaptic weights can be updated up to 1 MHz and that a resolution exceeding 14 bits can be attained. The test chips successfully perform XOR learning using each algorithm.

Real-time object detection or recognition technology becomes more important for various intelligent vision systems. Processing models for object detection or recognition from natural images should tolerate pattern deformations and pattern position shifts. The hierarchical convolutional neural networks are considered as a promising model for robust object detection/recognition. This model requires huge computational power for a large number of multiply-and-accumulation operations. In order to apply this model to robot vision or various intelligent real-time vision systems, its LSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose an LSI architecture based on this algorithm. As a proof of concept for our LSI architecture, we have designed, fabricated and tested two test LSIs: a sorting LSI and an image-filtering LSI. The sorting LSI is designed based on the content addressable memory (CAM) circuit technology. The image-filtering LSI is designed for parallel processing by analog circuit array based on the merged/mixed analog-digital approach. We have verified the validity of our LSI architecture by measuring the LSIs.

This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.

This paper proposes a new chaos generator circuit with a current sampling scheme. This circuit generates an arbitrary nonlinear function corresponding to the time-domain current waveform supplied from an external source by using a pulse phase modulation approach. The measurement results of a fabricated chip with TSMC 0.25 µm process technology demonstrate that the proposed circuit can generate chaos signals even if D/A conversion is used for nonlinear waveform generation, because a current integral by sampling with a short pulse smooths the quantized nonlinear function.

This paper describes the learning performance of the deterministic Boltzmann machine (DBM), which is a promising neural network model suitable for analog LSI implementation. (i) A new learning procedure suitable for LSI implementation is proposed. This is fully-on-line learning in which different sample patterns are presented in consecutive clamped and free phases and the weights are modified in each phase. This procedure is implemented without extra memories for learning operation, and reduces the chip area and power consumption for learning by 50 percent. (ii) Learning in a layer-type DBM with one output unit has characteristic local minima which reduce the effective number of available hidden units. Effective methods to avoid reaching these local minima are proposed. (iii) Although DBM learning is not suitable for mapping problems with analog target values, it is useful for analog data discrimination problems.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

This paper describes a parameter extraction system that can easily accommodate many MOSFET models. The model-adaptability is contributed by tow factors; a model-adaptable initial value estimation technique and an environment which stores and reuses extraction procedures. A designer can easily develop an extraction procedure for a new MOSFET model by modifying a procedure for another MOSFET model developed previously. We have verified that the system is suitable for major SPICE models.

An integrate-and-fire-type spiking feedback network is discussed in this paper. In our spiking neuron model, analog information expressing processing results is given by the relative relation of spike firing. Therefore, for spiking feedback networks, all neurons should fire (pseudo-)periodically. However, an integrate-and-fire-type neuron generates no spike unless its internal potential exceeds the threshold. To solve this problem, we propose negative thresholding operation. In this paper, this operation is achieved by a global excitatory unit. This unit operates immediately after receiving the first spike input. We have designed a CMOS spiking feedback network VLSI circuit with the global excitatory unit for Hopfield-type associative memory. The circuit simulation results show that the network achieves correct association operation.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.

This paper proposes a new method for image segmentation and extraction using nonlinear cellular networks. Flexible segmentation of complicated natural scene images is achieved by using resistive-fuse networks, and each segmented regions is extracted by nonlinear oscillator networks. We also propose a nonlinear cellular network circuit implementing both resistive-fuse and oscillator dynamics by using pulse-modulation techniques. The basic operation of the nonlinear network circuit is confirmed by SPICE simulation. Moreover, the 1010-pixel image segmentation and extraction are demonstrated by high-speed circuit simulation.

This paper proposes a new approach for the development of a module generator that can parameterize both the size and the structure of layout. The proposed method acquires a design procedure from the design process of a designer, and reuses it to synthesize new layouts with different input parameters that affect the size or the structure of layout. In this method, a designer creates a module layout on a layout editor instead of writing a program. From his design process, a procedure to synthesize the layout is automatically derived. Then, it is generalized so that it could be valid under different values of input parameters. The generalized procedure is independent of design rules, and is capable of synthesizing error-free module layouts of different size and structure. Also, the procedure includes designer's requirements on how the layout should be designed. The experimental results of applying the approach for developing generators of analog device components show effectiveness of our approach.

The concept of stochastic association has originally been proposed in relation to single-electron devices having stochastic behavior due to quantum effects. Stochastic association is one of the promising concepts for future VLSI systems that exceed the conventional digital systems based on deterministic operation. This paper proposes a CMOS stochastic associative processor using PWM (pulse-width modulation) chaotic signals. The processor stochastically extracts one of the stored binary patterns depending on the order of similarity to the input. We confirms stochastic associative processing operation by experiments for digit pattern association using the CMOS test chip.

We propose a motion detection model, which is suitable for higher speed operation than the video rate, inspired by the neuronal propagation in the hippocampus in the brain. The model detects motion of edges, which are extracted from monocular image sequences, on specified 2D maps without image matching. We introduce gating units into a CA3-CA1 model, where CA3 and CA1 are the names of hippocampal regions. We use the function of gating units to reduce mismatching for applying our model in complicated situations. We also propose a map-division method to achieve accurate detection. We have evaluated the performance of the proposed model by using artificial and real image sequences. The results show that the proposed model can run up to 1.0 ms/frame if using a resolution of 6460 units division of 320240 pixels image. The detection rate of moving edges is achieved about 99% under a complicated situation. We have also verified that the proposed model can achieve accurate detection of approaching objects at high frame rate (>100 fps), which is better than conventional models, provided we can obtain accurate positions of image features and filter out the origins of false positive results in the post-processing.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.