Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.

This paper presents a low distortion 3rd-order continuous-time delta-sigma modulator for a worldwide digital TV-receiver whose peak SNDR is 69.8 dB and SNR is 70.2 dB under 1 V power supply. To enhance SNDR performance, the mechanisms to occur harmonic distortions at feedback current-steering DAC and flash ADC have been analyzed. A low power tuning system using RC-relaxation oscillator has been developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing a very compact circuit. Reduction schemes of the distortions enabled the modulator to achieve FOM of 0.18 pJ/conv-step.

This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.

This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 µm-CMOS process. The total chip area of the PLL is reduced to 1/2 of the previous one. The jitter performance is almost equal to conventionally biased PLL.

This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um2 silicon area and consumes 0.18 mW at 1 GS/s.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.

This paper describes an oversampling analog-to-digital converter (ADC) suitable for PCM codes. Non-linear 5-level quantizer is implemented to noise-shaping modulator. This ADC meets the specifications of ITU-T G.712, in spite of using first order delta-sigma modulator, and realizes low power operation. This chip is fabricated in 0.8 µm double-poly and double-metal CMOS process and occupies a chip area of 15 mm2. Maximum power consumption is 12.8 mW with a single +3 V power supply including DAC and TONE generator.

In this paper, a CMOS data recovery PLL for DVD-ROM is described. Some techniques have been introduced to alleviate the specifications required to analog circuits. A new phase detector alleviates the timing specification of a delay line and a pulse generator. A new frequency detector increases the capture range up to 8% of the center frequency. We have achieved to realize the data recovery PLL that operates at DVD-ROMx14 speed.