This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.
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Shiro DOSHO, Takashi MORIE, Koji OKAMOTO, Yuuji YAMADA, Kazuaki SOGAWA, "A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 6, pp. 739-745, June 2006, doi: 10.1093/ietele/e89-c.6.739.
Abstract: This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.739/_p
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@ARTICLE{e89-c_6_739,
author={Shiro DOSHO, Takashi MORIE, Koji OKAMOTO, Yuuji YAMADA, Kazuaki SOGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit},
year={2006},
volume={E89-C},
number={6},
pages={739-745},
abstract={This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.},
keywords={},
doi={10.1093/ietele/e89-c.6.739},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 739
EP - 745
AU - Shiro DOSHO
AU - Takashi MORIE
AU - Koji OKAMOTO
AU - Yuuji YAMADA
AU - Kazuaki SOGAWA
PY - 2006
DO - 10.1093/ietele/e89-c.6.739
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.
ER -