Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

This paper discusses the design and performance of on-chip passive components of transmission lines (TR) and inductors. First, the measurement technique of on chip passives is discussed. A transmission line that can be used for Gbps signal propagation on Si CMOS is examined. As a high density transmission line structure of diagonal-pair differential TR line is described. Also, a circuit and TR line is introduced for above 10 Gbps signal propagation. The on-chip inductor which is a key passive component in RF application of Si CMOS technology is discussed. We examine some on-chip inductors that have been developed in our group: small area inductor, high performance inductor using WL-CSP (Wafer-Level Chip-Size-Packaging) technology. Finally, a wide tuning range LC-VCO using a variable inductor for RF reconfigurable circuit is introduced.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.

This paper proposes the combination of adjustable architecture and parameter optimization software, employing a method based on artificial intelligence (AI), to realize an image rejection mixer (IRM) that can enhance its image rejection ratio within a short period of time. The main components of the IRM are 6 Gilbert-cell multipliers. The tail current of each multiplier is adjusted by the optimization software, and the gain and phase characteristics are optimized. This adjustment is conventionally extremely difficult because the 6 tail currents to be adjusted simultaneously are mutually interdependent. In order to execute this adjustment efficiently, we employed a Genetic Algorithm (GA) that is a robust search algorithm that can find optimal parameter settings in a short time. We have successfully developed an IRM chip that has a performance of 71 dB and is suitable for single-chip integration with WCDMA applications.

Four 50% duty-cycle divide-by-3 prescalers--positively/ negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers--are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-µm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.

A LC oscillator based upon the quadrature magnetic coupling to generate a mutual negative resistance (mu-R) is introduced. The topology offers enhanced optimum phase noise at low supply voltages by enabling extended circuit operation in the current-limited regime through the control of its mutual inductors' coupling factor, k. The principal operation of the mu-R oscillator is described and its comparison with the popular cross-coupled topology is discussed. The capability of the technique is demonstrated via design examples of 1.8 GHz oscillators. Simulations show that, by employing inductors with a self-inductance of 2 nH, a quality factor of about 7.5 and a coupling k=0.52, the mu-R oscillator exhibits the minimum phase noise of -142 dBc/Hz at 3 MHz-offset with 18 mA bias current and 2 V supply. This is 3-dB more than the minimum achievable phase noise in the cross-coupled oscillator with identical component parameters and supply voltage level.

This paper describes a -90 dBc@10 kHz phase noise fractional-N frequency synthesizer of 110 M-180 MHz output with accurate loop bandwidth control. Stable phase noise characteristics are achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts voltage controlled oscillator (VCO) gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13 µm CMOS process shows stable and 6.8 dB improvement of the phase noise performance is achieved against process and environmental variations.

A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.

A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

This paper presents a novel gain boosted and bandwidth enhanced CMOS Op-Amp based on the well-known folded cascode structure. In contrast with the conventional methods which increase output resistance for gain boosting, the transconductance of the circuit is increased, therefore the -3 dB frequency is the same as for folded cascode structure. With negligible extra power consumption, the unity gain bandwidth is increased considerably. In this method, a new node is created in the circuit which introduces a pole to the transfer function with a frequency lower than cascode pole; feed-forward compensation is employed to reduce the effect of this pole on the frequency response. The input common mode range is limited slightly by 0.2-0.3 V with respect to folded cascode which is insensible. HSPICE simulations using level 49 parameters (BSIM3v3) in a typical 0.35 µm CMOS technology result in three times gain boosting and 60% enhancement in unity gain bandwidth compared to folded cascode, while the power consumption is increased by 10%.

Real-time object detection or recognition technology becomes more important for various intelligent vision systems. Processing models for object detection or recognition from natural images should tolerate pattern deformations and pattern position shifts. The hierarchical convolutional neural networks are considered as a promising model for robust object detection/recognition. This model requires huge computational power for a large number of multiply-and-accumulation operations. In order to apply this model to robot vision or various intelligent real-time vision systems, its LSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose an LSI architecture based on this algorithm. As a proof of concept for our LSI architecture, we have designed, fabricated and tested two test LSIs: a sorting LSI and an image-filtering LSI. The sorting LSI is designed based on the content addressable memory (CAM) circuit technology. The image-filtering LSI is designed for parallel processing by analog circuit array based on the merged/mixed analog-digital approach. We have verified the validity of our LSI architecture by measuring the LSIs.

We extend the adaptive-order rational Arnoldi algorithm for multiple-inputs and multiple-outputs (MIMO) interconnect model order reductions. Instead of using the standard Arnoldi algorithm for the SISO adaptive-order reduction algorithm (AORA), we study the adaptive-order rational global Arnoldi (AORGA) algorithm for MIMO model reductions. In this new algorithm, the input matrix is treated as a vector form. A new matrix Krylov subspace, generated by the global Arnoldi algorithm, will be developed by a Frobenius-orthonormal basis. By employing congruence transformation with the matrix Krylov subspace, the one-sided projection method can be used to construct a reduced-order system. It will be shown that the system moment matching can be preserved. In addition, we also show that the transfer matrix residual error of the reduced system can be derived analytically. This error information will provide a guideline for the order selection scheme. The algorithm can also be applied to the classical multiple point MIMO Pade approximation by the rational Arnoldi algorithm for multiple expansion points. Experimental results demonstrate the feasibility and the effectiveness of the proposed method.

A method using an averaging technique for the analysis and evaluation of real quasi-resonant converters (QRC's) is proposed in this paper. To reduce the great difference between the real characteristics and those of ideal circuits, a modeling technique is developed by considering the effect of parasitic power losses. Then, using the averaging approach reasonably simplifies the process of solving equations to obtain the steady-state solutions of state variables. Also, an updating algorithm is constructed to take all the power losses such as core losses, which are often absent in the conventional analysis, into account to improve the accuracy of the steady-state solutions. By these efforts, the evaluation of characteristics for QRC's is realized.

The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.

A new method to reduce power consumption of a linear transconductor is proposed in this paper. The minimum tail current for the operation of the transconductor is supplied by a new current source circuit. The proposed circuit is based on a dynamic biasing current technique. Results of SPICE simulation show that the proposed technique is very effective to reduce power consumption of the transconductor.

A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4N MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias affects the threshold voltage of transistors and improves performance of the structure.

High-resolution FMCW reflectometry is often realized by sampling the beat signal with a clock signal generated from an auxiliary interferometer. The drawback of this system is that the measurement range is limited to less than half of the optical path difference of the auxiliary interferometer to satisfy the Sampling theorem. We propose and demonstrate a method to extend the measurement range of the system. The clock signal gerenerated from the auxiliary interferometer is electronically frequency-multipled by using a PLL circuit. The measurement range is experimentally extended by a factor of 20 while keeping high spatial resolution, and is theoretically extended by a factor of 128. The advantage of the proposed system is that the optical path difference of the auxiliary interferometer can be kept short, which is very effective for obtaining the stable and low time-jitter clock signal.

In this paper, the confinement loss of octagonal photonic crystal fibers (PCFs) with an isosceles triangle lattice of air-holes are numerically investigated. Taking into account the confinement loss, the mode field diameter (MFD), the effective area (Aeff) and the chromatic dispersion of octagonal PCFs are calculated, compared to conventional hexagonal PCFs. It is found from confinement loss and MFD results that the octagonal PCFs can confine the field strongly than the hexagonal PCFs due to the different air filling fraction. Moreover, it is shown that the octagonal PCFs are obtained not only positive but also negative larger dispersion values and smaller Aeff values compared to the hexagonal PCFs.

Sleep transistors such as MTCMOS and SCCMOS drastically reduce leakage current, but their ON resistances cause significant performance degradation. Larger sleep transistors reduce their ON resistances, but increase leakage current in a sleep mode. Decoupling capacitors beside sleep transistors reduce leakage current. Experimental results show that PMOS SCCMOS with a 4 pF decoupling capacitor reduces leakage current by 1/673 on a 64 bit adder in a 90 nm process.

A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.

A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΣΔ) modulator is presented in this paper. The proposed ΣΔ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-µm double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.630.62 mm² and the power consumption is 17.5 mW.

Reduction of the intensity noise in semiconductor lasers is important subject to extend application range of the device. Blue-violet InGaN laser reveals high quantum noise when the laser is operated with low output power. The authors proposed a new scheme of noise reduction both for the optical feedback noise and the quantum noise by applying electric feedback which is positive type at a high frequency and negative type for lower frequency range. Noise reduction effect down to a level lower than the quantum noise was experimentally confirmed even under the optical feedback.

A simple method for the gain improvement of matrix distributed amplifiers is presented. The method is based on modifying the central transmission line of the matrix amplifier without any changes in the input and output transmission lines. In the new method the termination impedances in the central transmission line are modified and the transmission line is replaced by an impedance matching circuitry. It has been shown that the new method can significantly improve the gain while preserving the input and output return losses of the amplifier.

A novel first order voltage-mode non-inverting and inverting output of all-pass filter using an inverting type current conveyor (ICCII) is given. It is a first announced about a first-order voltage-mode non-inverting and inverting output of all-pass filter at the same configuration in the literature. The proposed circuit is verified using HSPICE simulation with attractive results.

This paper presents a new built-in current sensor (BICS) that detects defects using the current testing technique in CMOS integrated circuits. The proposed circuit is a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applicable in deep sub-micron process. The area overhead of the BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 µm standard CMOS technology.