A finite impulse response (FIR) core based on the cascoded class AB SI technique is presented for low power wireless transceivers. Accomplished through both architectural and circuit developments, the filter's features include high speed, low power consumption, small silicon area and compatibility with standard CMOS process. For feasibility and performance assessments, an 8-tap 16 MS/s SI FIR filter with 5-bit coefficients and a 31-tap 80 MS/s SI matched filter (MF) for despreading task in future WCDMA receivers are demonstrated via simulations.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the resistive tail-biased differential amplifier and the output stage relies upon the feed-forward class AB technique with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Analysis on the achievable peak voltage swing of the OTA when employed in filters is given. Simulation results of a 0.5-V 100-kHz elliptic 5th-order filter based on the OTA's in a 2-V 0.18 µm CMOS process indicate the differential peak voltage as large as 0.42 Vp (84% of the supply voltage) at 1% THD with the SFDR of 60 dB and the total power consumption of 50 µW.

The noise performances under AWGN channel of the IF-derivative and the quadrature differential FM discriminators, which are widely utilized in modern low power wireless radios, are analyzed and compared. The analysis relies upon the time-domain multi-sinusoidal representation of the noise that facilitates accurate and closed-form analytical SNR characteristics. Derivation of the SNR equations is detailed and discussion based on the analysis results is given to provide insights into the discriminators' performance limitation where it is demonstrated that the differential scheme is considerably more advantageous. Simulated SNR characteristics of practical continuous-phase frequency shift keying (CPFSK) systems using both the FM discriminators are presented as analysis verification.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

This paper presents an FPGA implementation of highly modular universal discrete transforms. The implementation relies upon the unified discrete Fourier Hartley transform (UDFHT), based on which essential sinusoidal transforms including discrete Fourier transform (DFT), discrete Hartley transform (DHT), discrete cosine transform (DCT) and discrete sine transform (DST) can be realized. It employs a reconfigurable, scalable and modular architecture that consists of a memory-based FFT processor equipped with pre- and post-processing units. Besides, a pipelining technique is exploited to seamlessly harmonize the operation between each sub-module. Experimental results based on Xilinx Virtex-II Pro are given to examine the performance of the proposed UDFHT implementation. Two practical applications are also shown to demonstrate the flexibility and modularity of the proposed work.

A structure of a track-and-hold (T/H) circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced. Its main features include low complexity, low operating supply voltage and gain insensitivity to device mismatches, leading to efficient realization of numerous baseband functions in modern communication systems. The detailed operation and performance analysis of the FG T/H circuit are given. Functional verification of the circuit is provided through a breadboard experiment. The effectiveness of the circuit is verified via simulations where the single T/H cell operating at 10 MHz clock frequency exhibits gain variation less than 0.13% and a dynamic range over 71 dB with the coupling capacitance of 300 fF at 1.5 V supply and 12.75 µW power consumption. As a demonstration on its practical viability, the designed FG T/H cell was also utilized to realize a 10 MS/s 7-tap analog correlator for possible use in modern communication applications.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz+55 kHz) respectively. The filter consumes total power consumption of 60 µW.

A new technique to reduce the isolation network's size in a Marchand balun needed for perfect all-port matching and isolation is proposed. The proposed isolation circuit is realized using a coupled-line phase-inverter in place of the bulky 180line section that has been previously proposed. Analysis of the proposed circuit yields the required relationship between coupling coefficient and electrical length of the coupler. Based on the design equations, the circuit is experimentally demonstrated at 1.8 GHz and has shown excellent results. The obtained output return loss and isolation loss are more than 18 dB and 40 dB, respectively. The proposed balun was then applied to the application of a doubled-balanced ring-diode mixer. The designed mixer achieves a low conversion loss of 6 dB at its operating frequency, which is 1.5 dB lower than for a doubled-balanced diode mixer using a conventional impedance-transforming Marchand balun. The RF-IF and LO-IF isolations are well below 25 dB and 18 dB across 1 GHz RF operating bandwidth, respectively.

A double-capacitor phase error compensation configuration is proposed for Gm-C and MOSFET-C filters. The use of two capacitors enables the effective compensation capacitance to track with the tuning resistance, thereby making it more effective over a wider frequency tuning range as compared to the conventional single-capacitor configuration. Simulations of 5th-order Chebyshev filters in a 0.18 µm CMOS process with more than one octave tuning range were carried out to demonstrate the viability of the proposed double-capacitor configuration for both Gm-C and MOSFET-C filters.

A LC oscillator based upon the quadrature magnetic coupling to generate a mutual negative resistance (mu-R) is introduced. The topology offers enhanced optimum phase noise at low supply voltages by enabling extended circuit operation in the current-limited regime through the control of its mutual inductors' coupling factor, k. The principal operation of the mu-R oscillator is described and its comparison with the popular cross-coupled topology is discussed. The capability of the technique is demonstrated via design examples of 1.8 GHz oscillators. Simulations show that, by employing inductors with a self-inductance of 2 nH, a quality factor of about 7.5 and a coupling k=0.52, the mu-R oscillator exhibits the minimum phase noise of -142 dBc/Hz at 3 MHz-offset with 18 mA bias current and 2 V supply. This is 3-dB more than the minimum achievable phase noise in the cross-coupled oscillator with identical component parameters and supply voltage level.