This paper presents an FPGA implementation of highly modular universal discrete transforms. The implementation relies upon the unified discrete Fourier Hartley transform (UDFHT), based on which essential sinusoidal transforms including discrete Fourier transform (DFT), discrete Hartley transform (DHT), discrete cosine transform (DCT) and discrete sine transform (DST) can be realized. It employs a reconfigurable, scalable and modular architecture that consists of a memory-based FFT processor equipped with pre- and post-processing units. Besides, a pipelining technique is exploited to seamlessly harmonize the operation between each sub-module. Experimental results based on Xilinx Virtex-II Pro are given to examine the performance of the proposed UDFHT implementation. Two practical applications are also shown to demonstrate the flexibility and modularity of the proposed work.

This paper proposes an adaptive antenna using a combination of on-off and CMA algorithms. With the proposed technique, the on-off algorithm is first employed to search for a desired signal direction in which maximum received power is achieved. Then, interference is suppressed by performing CMA. Simulations are conducted according to the potential application of the proposed adaptive antenna. The simulation results show the SINR improvement implying that the proposed adaptive antenna can be applied to microwave RFID systems in order to resolve reader collision. Furthermore, the proposed adaptive antenna is implemented and then experimented. The experimental results verify that the proposed adaptive antenna can reduce interference resulting in the collision problem.

A finite impulse response (FIR) core based on the cascoded class AB SI technique is presented for low power wireless transceivers. Accomplished through both architectural and circuit developments, the filter's features include high speed, low power consumption, small silicon area and compatibility with standard CMOS process. For feasibility and performance assessments, an 8-tap 16 MS/s SI FIR filter with 5-bit coefficients and a 31-tap 80 MS/s SI matched filter (MF) for despreading task in future WCDMA receivers are demonstrated via simulations.

This paper presents a multiple constrained subspace based multiuser detector for synchronous long-code downlink multirate DS-CDMA systems. The novel receiver adapts its fractionally-spaced equaliser tap-weights based upon two modes, namely training and decision-directed modes. Switching between two modes is achieved by changing the code constraint in the associated subspace algorithm. Moreover, detection of the desired user requires the knowledge of the desired user's spreading code only. Simulation results show that the proposed receiver is capable of multiple access interference (MAI) suppression and multipath mitigation. Besides, the results reveal the improvement in terms of convergence speed and mean square error (MSE) of the proposed receiver over the existing receiver in both static and dynamic environments.