In this paper, a fault model for multiple-valued programmable logic arrays (MV-PLAs) is proposed and the equivalences of faults of MV-PLA's are discussed. In a supposed multiple-valued NOR/TSUM PLA model, it is shown that multiple-valued stuck-at faults, multiple-valued bridging faults, multiple-valued threshold shift faults and other some faults in a literal generator circuit are equivalent or subequivalent to a multiple crosspoint fault in the NOR plane or a multiple fault of weights in the TSUM plane. These results lead the fact that multiple-valued test vector set which indicates all multiple crosspoint fault and all multiple fault of weights also detects above equivalent or subequivalent faults in a MV-PLA.

Some of the recent digital systems have a serious clock skew problem due to huge hardware implementation and high-speed operation in VLSI's. To overcome this problem, clock distribution techniques and, more notably, asynchronous system design methodologies have been investigated. Since the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present a design of asynchronous digital system which is based on B-ternary logic that can process binary data. The system which is based on speed-independent mode consists of data-path and its controller. Then we provide B-ternary two-phase binary data processing in the data-path and its control procedure with hand-shake protocol. To implement the system some functional elements are presented, that is, a ternary-in/binary-out register with request/acknowledge circuits and a control unit. These functional elements are fabricated with ternary NOR, NAND, INV gates and ternary-in/binary-out D-FF (D-elements). The B-ternary based asynchronous circuit has less interconnections, achives race-free operations and makes use of conventional binary powerful design tools. Particularly, we extend the speed-independent delay model to relativity delays in order to reduce hardware overhead of checking memory stability in the system. As a concrete example, a carry-completion type asynchronous adder system is demonstrated under extended speed-independent mode to show the validity of the extension.

In this paper, a new optimum input encoding algorithm with m-out-of-2m code which is called Half-Hot Code is presented. By applying Half-Hot Code to the input encoding in PLA-based digital system, the logic functions of the system turn out to be unate functions, thus, the number of bit-lines of PLA may be reduced. The proposed method further reduces the number of product-lines of PLA optimally. In this code assignment procedure, computed Boolean subspaces satisfying suggeset two conditions are assigned to each partitioned subset of digital input variables which are obtained by disjoint minimization or other techniques. As an experiment to evaluate the method, the state assignment for finite state machines of two-lavel implementation is considered. Specifically, the proposed Half-Hot Code assignment is compared with arbitrary Half-Hot Code assignment. The results show that the optimum encoding is superior to an arbitrary assignment up to about 24% in the number of product-lines of PLA.

In this paper, the confinement loss of octagonal photonic crystal fibers (PCFs) with an isosceles triangle lattice of air-holes are numerically investigated. Taking into account the confinement loss, the mode field diameter (MFD), the effective area (Aeff) and the chromatic dispersion of octagonal PCFs are calculated, compared to conventional hexagonal PCFs. It is found from confinement loss and MFD results that the octagonal PCFs can confine the field strongly than the hexagonal PCFs due to the different air filling fraction. Moreover, it is shown that the octagonal PCFs are obtained not only positive but also negative larger dispersion values and smaller Aeff values compared to the hexagonal PCFs.

In this paper, a new encoding/decoding scheme of multiple-valued separable balanced codes is presented. These codes have 2m information digits and m (R - 2) check digits in radices R 4, 2m - 1 information digits and m + 1 check digits in R = 3, where code-length n = Rm. In actual use of code-lengths and radices, it is shown that the presented codes are relatively efficient in comparison with multiple-valued Berger codes which are known as optimal unordered codes. Meanwhile, the optimality of multiple-valued Berger codes is discussed.