All-Digital Clock Deskew Buffer with Variable Duty Cycles
Summary :
An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.753-760
- Publication Date
- 2006/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.6.753
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
- Category
Authors
Keyword
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Shao-Ku KAO, Shen-Iuan LIU, "All-Digital Clock Deskew Buffer with Variable Duty Cycles" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 6, pp. 753-760, June 2006, doi: 10.1093/ietele/e89-c.6.753.
Abstract: An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.753/_p
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@ARTICLE{e89-c_6_753,
author={Shao-Ku KAO, Shen-Iuan LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={All-Digital Clock Deskew Buffer with Variable Duty Cycles},
year={2006},
volume={E89-C},
number={6},
pages={753-760},
abstract={An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.},
keywords={},
doi={10.1093/ietele/e89-c.6.753},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - All-Digital Clock Deskew Buffer with Variable Duty Cycles
T2 - IEICE TRANSACTIONS on Electronics
SP - 753
EP - 760
AU - Shao-Ku KAO
AU - Shen-Iuan LIU
PY - 2006
DO - 10.1093/ietele/e89-c.6.753
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.
ER -
English
