IEICE TRANSACTIONS on Electronics
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Area-efficient Binarized Neural Network Inference Accelerator Based on Time-multiplexed XNOR Multiplier Using Loadless 4T SRAM
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- Publication
- IEICE TRANSACTIONS on Electronics Vol.0 No.0 pp.0-0
- Publicized
- 2024/05/08
- DOI
- 10.1587/10.1587/transele.2023ECP5051
- Type of Manuscript
- PAPER
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Yihan ZHU, Takashi OHSAWA, "Area-efficient Binarized Neural Network Inference Accelerator Based on Time-multiplexed XNOR Multiplier Using Loadless 4T SRAM" in IEICE TRANSACTIONS on Electronics,
vol. , no. 0, pp. 0-0, January , doi: 10.1587/10.1587/transele.2023ECP5051.
Abstract:
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2023ECP5051/_advpub_f
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@ARTICLE{2023ECP5051,
author={Yihan ZHU, Takashi OHSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Area-efficient Binarized Neural Network Inference Accelerator Based on Time-multiplexed XNOR Multiplier Using Loadless 4T SRAM},
year={},
volume={},
number={0},
pages={0-0},
abstract={},
keywords={},
doi={10.1587/10.1587/transele.2023ECP5051},
ISSN={},
month={January},}
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TY - JOUR
TI - Area-efficient Binarized Neural Network Inference Accelerator Based on Time-multiplexed XNOR Multiplier Using Loadless 4T SRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 0
EP - 0
AU - Yihan ZHU
AU - Takashi OHSAWA
PY -
DO - 10.1587/10.1587/transele.2023ECP5051
JO - IEICE TRANSACTIONS on Electronics
SN -
VL -
IS - 0
JA - IEICE TRANSACTIONS on Electronics
Y1 - January
AB -
ER -
English
