In this paper, two synthesis methods of fuzzy membership function circuits with multiple inputs are proposed. By using bounded-differences expressions, membership function representations suitable for logic circuits in current mode is obtained. In bounded-difference expressions, bounded-difference, switch function and algebraic sum are used. Since these operations can be realized by MOS current-mirrors, MOS pass-transistors and wired-sum connections, the membership function circuits with multiple inputs can be built with these circuit elements. Therefore the synthesized circuits can be implemented in MOS IC forms. The potential applications of the membership function circuits with multiple inputs are real-time inference engine and fuzzy ROM.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

A CMOS fully balanced current-mode filter is presented. A fully balanced current-mode integrator which is the basic building block is implemented by adding a very simple common-mode-rejection mechanism to fully differential one. The fully balanced operation can eliminate even order distortion, which is one of the drawbacks in previous continuous current-mode filter. Moreover, the additional circuit can work as not only common-mode-rejection mechanism but also Q-tuning circuit which compensates lossy elements due to finite output impedance of MOS FET. A prototype fifth-order low-pass lad-der filter designed in a standard digital 0.8µm CMOS process achieved a cut-off frequency (fC) of 100MHz; fC was tunable from 75MHz to 120MHz by varying a reference bias current from 50µA to 150µA. Using a single 3V power supply with a nominal reference current of 100µA, power dissipation per one pole is 30mW. The active filter area was 0.011mm2/pole and total harmonic distortion (THD) was 0.73 [%] at 80MHz, 80µA amplitude signal. Furthermore, by adjusting two bias currents, on chip automatic both frequency and Q controls are easily implemented by typical tuning systems, for example master-slave tuning systems [1].

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.

It have been one open and significant topic for real-time applications to enhance the processing-speed of Boltzmann machines for long time. One effective way of solution of this problem is the augmentation of probability of neurons' state move. In this paper, a novel method, called a rejectionless method, was proposed and introduced into the Boltzmann machines for this augmentation. This method has a feature of independence on the ratio of neurons' state move. The efficiency of this method for speed-up was confirmed with the experiments of TSP and graph problem.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

Intelligent robot control systems based on multiprocessors, sensors, and actuators require a flexible network for communicating various types of real-time data (e.g. sensing data, interrupt signals). Furthermore, serial data transfer implemented using a few wiring lines is also required. Therefore, a CDMA serial communication interface with a new two-step synchronization technique is proposed to counter these problems. The transmitter and receiver fabricated by 0.25 µm digital CMOS technology achieve 2.7 Gcps (gigachips per second) and can multiplex 7 communication channels.

This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

A maximum and a minimum circuits with multiple inputs are proposed. The operating speeds of these circuits are independent of the number of the inputs. Since the proposed circuits consist of only NMOS transistors, they can be implemented in semi-custom IC forms. A potential application of these circuits is a real-time fuzzy controller.

A fuzzy microprocessor is developed using 1.2 µm CMOS process. The inference scheme for the if-then fuzzy rules consists of three main steps i. e. if-part process, then-part process and defuzzification. In order to realize very high-speed inference and moderate programmability, we introduce three-type different structures i.e. SIMD, logic-in-memory and Wallace tree structures which are suitable for the three main steps. The inference speed including defuzzification is 7.5 MFLIPS which is 12.9 times higher than the previous VLSI implementation, and it can carry out many rules (960 rules) and many input and output variables (16 variables).