Switched capacitor (SC) circuits for realizing piecewise-linear S- and Z-shaped variable threshold functions are proposed. With these circuits, basic nonlinear functions in fuzzy logic and neural networks can be synthesized in the form suitable for MOS VLSIs.

This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.

In this paper, a novel chaos circuit with long working-life is proposed. The proposed circuit consists of NMOS-coupled discrete-time chaotic cell circuits. By employing chaos synchronization phenomenon, the proposed circuit can achieve long working-life. Since the proposed circuit is less susceptible to breakdown, the rate of the acceptable product for chaos IC can be improved. Furthermore, thanks to the coupling by using NMOSFET's, the loss of the connection line between chaotic cell circuits can be controlled electronically. Therefore, the proposed system designed by using switched-current (SI) techniques is useful as an experimental tool to analyze chaos synchronization phenomena. The validity of the proposed circuits is confirmed by computer simulations and experiments.

in this paper, the steady-state and dynamic analyses of the continuous and the discontinuous conduction mode of the uk converter with nonzero mutual inductance by the state-space averaging method are described. For the analysis of the discontinuous conduction mode of the uk converter, the critical duty ratio is used. The analysis of the dynamic responses is presented for both the open- and closed-loop cases. The obtained results are useful for the optimum design of the uk converters.

In this paper, two synthesis methods of fuzzy membership function circuits with multiple inputs are proposed. By using bounded-differences expressions, membership function representations suitable for logic circuits in current mode is obtained. In bounded-difference expressions, bounded-difference, switch function and algebraic sum are used. Since these operations can be realized by MOS current-mirrors, MOS pass-transistors and wired-sum connections, the membership function circuits with multiple inputs can be built with these circuit elements. Therefore the synthesized circuits can be implemented in MOS IC forms. The potential applications of the membership function circuits with multiple inputs are real-time inference engine and fuzzy ROM.

In this work, we introduce a fuzzy inference in conventional backpropagation learning algorithm, for networks of neuron like units. This procedure repeatedly adjusts the learning parameters and leads the system to converge at the earliest possible time. This technique is appropriate in a sense that optimum learning parameters are being applied in every learning cycle automatically, whereas the conventional backpropagation doesn't contain any well-defined rule regarding the proper determination of the value of learning parameters.

A low sensitivity high-Q band-pass switched-capacitor (SC) filter with zero worst-case sensitivity at every arttenuation zero is proposed. The proposed SC filter is synthesized using parasitic-insensitive SC integrators with reduced capacitance spread.

An AC-DC converter using a new switched-capacitor (SC) transformer and its design are presented. The features of this circuit are as follows. (1) The maximum voltage of capacitors is 1/n times that of a condenser-input-type rectificer circuit, where n is the number of chargetransfer capacitors. (2) The output voltage ripple is small, since the equivalent smoothing capacitor value is n times that of conventional SC transformers (series-parallel switching type). Using the presented design method, each element value is designed from the specifications of a test circuit. The experimental results of the test circuit show that (1) the efficiency of the SC transformer is very high (95%), and the total efficiency is 74% due to the losses of the clock generator and the control circuit, (2) the maximum output power is 40 W, (3) the value of the inrush current of the tested converter is only twice the value of the steady state current. The measured characteristics showed good agreement with the calculated ones.

An integrator using UGB (unity-gain buffer) is proposed. The UGB has gain error. To improve the gain error of UGB in the integrator, a compensation technique of the gain error of UGB is proposed. Next, second-order ΣΔ A/D converter using UGB integrator with gain-error compensator is proposed. In the proposed circuit, the influence of input-output characteristic is simulated. In the simulation results, the improvement is confirmed. In addition, performance limiting factors due to non ideal effects, e.g., parasitic capacitance and offset voltage, are considered. Validity of the proposed compensation technique for each factor is confirmed in the simulation results.

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

Two kinds of cyclic switched-capacitor A/D converters using only one Op-Amp are presented. The effects of the nonidealities of the circuit such as a capacitor-ratio mismatch, an Op-Amp's offset voltage, and a parasitic capacitance, on a conversion accuracy are discussed.

A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.

A new MOS linear operational transconductance amplifier (OTA) for the up-to-4 MHz range OTA-C filters is proposed. The proposed OTA is designed using a new linearizing technique based on bias-current modulation, to compensate nonlinearities in the transfer characteristic of the conventional current-source-biased source-coupled pair. The design and SPICE simulation are presented in detail, assuming the implementation by the typical p-well CMOS process. The simulation of a 3.58 MHz OTA-C band-pass filter built with the proposed OTAs showed close agreement with the desired performance.

Two algorithms are presented for a time-domain analysis of a switching converter which is replaceable with a piecewise-linear system. One of them is for the transient state analysis and the other is for the steady-state analysis. Both of them use the eigen-value and the eigen-vector calculations. The analysis based on these algorithms can be carried out more rapidly and accurately than the conventional analysis using standard fixed or variable step-size integration methods. On the uk converter, the results of the proposed method are compared with those of the Hamming method (a variable step integration method) and of SPICE2 (a general-purpose circuit analysis program using variable step-size integration method).

A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.

Three types of momentary power-failure detectors are presented here. These are commonly adopting novel type time-to-voltage (T-V) conversion which is realized by using switched-capacitor (SC) integrators. They can monitor and detect power failures lasting more than one cycle of an AC power source. Then they active a signal and start to generate auxiliary pulses synchronized to the AC power frequency through the power failure time. Their operating frequency ranges are from several tens Hz to several kHz covering almost AC power source frequencies, without any adjustment. The period of the auxiliary pulses is confirmed to be very stable as experimental results.

A new type of variable-gain amplifier employing two first-quadrant multiplier/dividers is discussed. It has many distinctive features, such as 1) no change in input and output impedances, when gain is changed, 2) good linearity insensitive to the area-mismatch of transistors, 3) zero ouput offset independent of ambient temperature and gain, 4) large gain-bandwidth product, 5) simple circuit configuration.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

A simple configuration of first-quadrant analog multiplier/divider has been applied to an R. M. S. -D. C. converter. The output voltage of the R. M. S. -D. C. converter is in good proportion to the true R. M. S. value for a D. C., a sine wave, a square wave, a triangular wave and pulse trains. The error is within 1% of full scale.

An n-th power function generator and an n-th rooter have been implemented in current mode. They exhibit good thermal stability and accuracy.