Current-Mode CMOS-Based Decoder with Redundantly Represented O Addend Method for Multiple-Radix Signed-Digit Number

Toru TABATA; Fumio UENO

Current-Mode CMOS-Based Decoder with Redundantly Represented O Addend Method for Multiple-Radix Signed-Digit Number

Toru TABATA, Fumio UENO

Full Text Views

0

Cite this

Summary :

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.6 pp.1002-1008

Publication Date: 1997/06/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))

Category

Cite this

Copy

Toru TABATA, Fumio UENO, "Current-Mode CMOS-Based Decoder with Redundantly Represented O Addend Method for Multiple-Radix Signed-Digit Number" in IEICE TRANSACTIONS on Fundamentals, vol. E80-A, no. 6, pp. 1002-1008, June 1997, doi: .
Abstract: We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_6_1002/_p

Copy

@ARTICLE{e80-a_6_1002,
author={Toru TABATA, Fumio UENO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Current-Mode CMOS-Based Decoder with Redundantly Represented O Addend Method for Multiple-Radix Signed-Digit Number},
year={1997},
volume={E80-A},
number={6},
pages={1002-1008},
abstract={We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.},
keywords={},
doi={},
ISSN={},
month={June},}

Copy

TY - JOUR
TI - Current-Mode CMOS-Based Decoder with Redundantly Represented O Addend Method for Multiple-Radix Signed-Digit Number
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1002
EP - 1008
AU - Toru TABATA
AU - Fumio UENO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1997
AB - We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.
ER -