A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Kyoko TSUKANO, Takahiro INOUE, Shoichi KOGA, Fumio UENO, "A New CMOS Neuron Circuit Based on a Cross-Coupled Current Comparator Structure" in IEICE TRANSACTIONS on Fundamentals,
vol. E75-A, no. 7, pp. 937-943, July 1992, doi: .
Abstract: A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_7_937/_p
Copy
@ARTICLE{e75-a_7_937,
author={Kyoko TSUKANO, Takahiro INOUE, Shoichi KOGA, Fumio UENO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New CMOS Neuron Circuit Based on a Cross-Coupled Current Comparator Structure},
year={1992},
volume={E75-A},
number={7},
pages={937-943},
abstract={A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A New CMOS Neuron Circuit Based on a Cross-Coupled Current Comparator Structure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 937
EP - 943
AU - Kyoko TSUKANO
AU - Takahiro INOUE
AU - Shoichi KOGA
AU - Fumio UENO
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 1992
AB - A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.
ER -