A new current-mode analog BiCMOS multiplier/divider circuit based on the translinear principle is presented. This circuit can be implemented by a standard 0.8µm BiCMOS process. The simulation results showed that the circuit realizes the high-speed and high-precision operation with a 3V supply.

Discrete-time chaotic circuits realizing a tent map and a Bernoulli map are synthesized using switched-current (SI) techniques. For these proposed circuits, simulations are performed concerning the return maps and bifurcation trees. The theoretical analysis is carried out to predict the bifurcation tree under the existence of the nonidealities in the return map. This analysis has been done by assuming the return maps to be piecewise linear. The proposed circuits are built with commerciallyavailable IC's. And their return maps and bifurcation trees are measured in the experiment. The design formulas are obtained for the bifurcation trees and they are confirmed by the simulation results. The proposed circuits are integrable by a standard BiCMOS technology.

A new CMOS neuron circuit suitable for VLSI implementation of artificial neural networks is proposed. A cross-coupled current comparator structure is adopted to obtain large differential neuron signals for high-speed multi-input/multi-output neuron operations. In addition, the shape of the output function of the proposed neuron circuit can be modified by simply varying the value of the auxiliary current sources. To estimate the performance of the proposed circuit as an element in a neural network, a 15-bit associative memory based on the Hopfield neural network was designed. The performances of a single 7-input neuron and of the 15-neuron associative memory are confirmed by SPICE simulations.

A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.