IEICE TRANSACTIONS on Electronics
Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems
Summary :
This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.10 pp.1275-1280
- Publication Date
- 1992/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Kazutaka TANIGUCHI, Fumio UENO, Takahiro INOUE, Toshitsugu YAMASHITA, "Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 10, pp. 1275-1280, October 1992, doi: .
Abstract: This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_10_1275/_p
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@ARTICLE{e75-c_10_1275,
author={Kazutaka TANIGUCHI, Fumio UENO, Takahiro INOUE, Toshitsugu YAMASHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems},
year={1992},
volume={E75-C},
number={10},
pages={1275-1280},
abstract={This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1275
EP - 1280
AU - Kazutaka TANIGUCHI
AU - Fumio UENO
AU - Takahiro INOUE
AU - Toshitsugu YAMASHITA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 1992
AB - This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.
ER -
English
