IEICE TRANSACTIONS on transactions
A High-Accuracy Switched-Capacitor Pipelined Analog-to-Digital Converter
Summary :
A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E72-E No.12 pp.1285-1291
- Publication Date
- 1989/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
- Category
- Analog Signal Processing
Authors
Keyword
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Fumio UENO, Takahiro INOUE, Shinji ARAKI, Kenichi SUGITANI, "A High-Accuracy Switched-Capacitor Pipelined Analog-to-Digital Converter" in IEICE TRANSACTIONS on transactions,
vol. E72-E, no. 12, pp. 1285-1291, December 1989, doi: .
Abstract: A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e72-e_12_1285/_p
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@ARTICLE{e72-e_12_1285,
author={Fumio UENO, Takahiro INOUE, Shinji ARAKI, Kenichi SUGITANI, },
journal={IEICE TRANSACTIONS on transactions},
title={A High-Accuracy Switched-Capacitor Pipelined Analog-to-Digital Converter},
year={1989},
volume={E72-E},
number={12},
pages={1285-1291},
abstract={A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A High-Accuracy Switched-Capacitor Pipelined Analog-to-Digital Converter
T2 - IEICE TRANSACTIONS on transactions
SP - 1285
EP - 1291
AU - Fumio UENO
AU - Takahiro INOUE
AU - Shinji ARAKI
AU - Kenichi SUGITANI
PY - 1989
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E72-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1989
AB - A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.
ER -
English
