An approach is described to synthesis and recognition of temporal patterns by using neural networks. A neural network is trained to produce prescribed waveforms with the steepest descent method which optimizes analog dynamics of neural networks described by differential equations. First a technique is developed for calculating error sensitivities with respect to network parameters by the adjoint network approach. Next an upper bound on timesteps is established to ensure the stability of the numerical solutions of the differential equations of networks. The effectiveness of these techniques are verified by several examples of learning of transient or oscillating waveforms with simple networks. In addition the complexity of the waveform is discussed which can be synthesized by a simple class of neural networks.

Recently, the hardware realizations of the neural networks for specially-purposed-use have been in focus. In this paper, two kinds of networks, a two-layer network and the Boltzmann machine, using the switched-capacitor circuit are proposed. The variable synaptic weights of neural circuit are realized by through the programmable capacitor array (PCA) in the switched-capacitor variable-coefficients multiplier. As a result, the recognition system of the handwritten character using a two-layer neural network is constructed by the discrete electronic elements and its desirable effects are shown by the experimental results. The stochastic operation in the processing element (PE) of the Boltzmann machine is realized by using the generation of noise voltage with the random number and is also confirmed by teh experimental results using the discrete electronic elements. Furthermore, the operations of the PE have been also confirmed by using the simulation of Traveling-Salesman Problem.

A priori estimation is presented for a computational complexity of the homotopy method applying to a certain class of uniquely solvable nonlinear equations. In the first place, the reason is explained why a computational complexity of the homotopy method can not be a priori estimated in general. In this paper, the homotopy algorithm is considered in which a numerical path following algorithm is executed based on the simplified Newton method. Then by introducing Urabe's theorem, which gives a sufficient condition guaranteeing the convergence of the simplified Newton method, it is shown that a computational complexity of the algorithm can be a priori estimated, when it is applied to a certain class of uniquely solvable nonlinear equation. In this paper, two types of path following algorithms are considered, one with a numerical error estimation in the domain of a nonlinear operator and another with one in the range of the operator.

In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.

This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.

Three types of momentary power-failure detectors are presented here. These are commonly adopting novel type time-to-voltage (T-V) conversion which is realized by using switched-capacitor (SC) integrators. They can monitor and detect power failures lasting more than one cycle of an AC power source. Then they active a signal and start to generate auxiliary pulses synchronized to the AC power frequency through the power failure time. Their operating frequency ranges are from several tens Hz to several kHz covering almost AC power source frequencies, without any adjustment. The period of the auxiliary pulses is confirmed to be very stable as experimental results.

A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.

An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.

Location theory on networks is concerned with the problem of selecting the best location in a specified network for facilities. In networks, the distance is an important measure to quantify how strongly related two vertices are. Mereover, the capacity between two vertices is also an important measure. In this paper, we define the location problems called the p-center problem, the r-cover problem and the p-median problem on undirected flow networks. We propose polynomial time algorithms to solve these problems.

This paper proposes an algorithm for optimizing concurrent program specification generated by design automation techniques. Some of the information in automatically generated specifications can be modified for optimization. The proposed algorithm changes some signals between processes. The computational complexity of the algorithm is O(nlogn), where n is the number of states in a given process specification. Experimental application results demonstrate it useful not only to optimize individual process descriptions but also to change signals transferred between processes in the optimization.

Both Petri nets and temporal logic have been widely used to specify concurrent programs. Petri nets appropriate to specify the behavioral structures of programs explicitly, while temporal logic is appropriate to specify the properties and constraints of programs. Since one can complement the other, using a combination of Petri nets and temporal logic is a highly promising approach to analyze, verify and synthesize concurrent programs. For the purpose of automatic program verification and synthesis, the emptiness problem (i.e., wheter a legal firing transition sequence satisfying a given temporal logic formula on a given Petri net exists) must be decidable. This paper reports a class to combine Petri nets and temporal logic as an infinite language and whose emptiness problem is decidable. We then show how to verify concurrent programs, using Petri nets and temporal logic, and also propose a compositional synthesis method that tune up reusable program components to satisfy a temporal logic specification.

A novel optical signal splitting method using a holographic transmission grating is proposed for optical communication use. An input beam from a SM-fiber is variably split into two output SM-fibers. Its applicability to the bit-error-free switching of a 1.8 Gbit/s signal is successfully demonstrated.

A new way to reduce the linewidth enhancement factor of Distributed Reflector dynamic-single-mode (DR-DSM) lasers is proposed, which is detuning of lasing wavelength from the Bragg wavelength. The linewidth enhancement factor αof DR-DSM laser was found to be reduced to half of medium defined value α_medium when the phase shift value between the active and the passive distributed reflectors is 0.25π.

A multichannel crossover switching network using interconnection channels of collimated lights is proposed and demonstrated. Diffraction losses of the switching network are theoretically estimated.

An active optical RS flip-flop based on bistability is proposed and demonstrated. The flip-flop employs a parallel symmetrical circuit with a constant current source. The switching speed of signal is improved and the structure is simplified furthermore.

In this paper, autonomous 3rd order Josephson junction circuits containing angular variable are analyzed. For the sake of simplicity, easiness and accuracy the piecewise linearizing approximation is emplyed here. Using this method, Poincaré map, bifurcation diagram, attractor dimension and Lyapunov spectrum have been efficiently obtained especially for the chaos in this system. We have also observed the almost one-dimensional feature of the chaos orbit and the fine structure of the chaos oscillation. This chaos has a low attractor dimension nearly equal to that for the quasi-periodic oscillation in non-autonomous 2nd order JJ circuits.

A novel strip representation of flat plate is proposed for the bistatic radar cross section (RCS) analysis. Direction of every strip is determined so that the Keller cone at any point may include the observer. A unique set of strips are determined for given directions of incidence and observer. This method is capable of covering all the directions of observer including that of specular reflection. The high accuracy of this method is demonstrated by comparing it with the exact or the moment method solutions for diffraction from a flat disk and a square plate.