IEICE TRANSACTIONS on transactions
A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic
Summary :
A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.12 pp.1973-1978
- Publication Date
- 1990/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
- Category
- VLSI Design
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Keyword
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Kunio NAKAGURO, Kunihiro ASADA, "A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 12, pp. 1973-1978, December 1990, doi: .
Abstract: A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_12_1973/_p
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@ARTICLE{e73-e_12_1973,
author={Kunio NAKAGURO, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on transactions},
title={A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic},
year={1990},
volume={E73-E},
number={12},
pages={1973-1978},
abstract={A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Design Method of Pseudo-Self-Checking LSI System Using Cascode Voltage Switch Logic
T2 - IEICE TRANSACTIONS on transactions
SP - 1973
EP - 1978
AU - Kunio NAKAGURO
AU - Kunihiro ASADA
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1990
AB - A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.
ER -
English
