A novel design concept for pseudo-self-checking CMOS LSI is presented, where cascode voltage switch logic (CVSL) gates are utilized as two-rail logic elements accompanied by simple exclusive OR testable checker sircuits. The concept is described for both static and dynamic CVSL circuits. Fault-detection signals of the element CVSL gates are monitored by an nMOS-like OR tree, which consumes static power only when a fault is detected. The checking tree is neither dual nor two rail circuit for simplicity, the self-checking property of which is achieved by periodic testing. (we call it pseudo-selft-checking circuit) Through analytical comparison and comparison by examples, it has found that the hardware increase in terms of transistor number is less than 30%, compared with standard static CMOS design without self-checking capability.