IEICE TRANSACTIONS on transactions
Hierarchical Decomposition for Circuit Simulation by Direct Method
Summary :
In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.12 pp.1948-1956
- Publication Date
- 1990/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
- Category
- Nonlinear Circuits and Simulation
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Masakatsu NISHIGAKI, Nobuyuki TANAKA, Hideki ASAI, "Hierarchical Decomposition for Circuit Simulation by Direct Method" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 12, pp. 1948-1956, December 1990, doi: .
Abstract: In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_12_1948/_p
Copy
@ARTICLE{e73-e_12_1948,
author={Masakatsu NISHIGAKI, Nobuyuki TANAKA, Hideki ASAI, },
journal={IEICE TRANSACTIONS on transactions},
title={Hierarchical Decomposition for Circuit Simulation by Direct Method},
year={1990},
volume={E73-E},
number={12},
pages={1948-1956},
abstract={In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Hierarchical Decomposition for Circuit Simulation by Direct Method
T2 - IEICE TRANSACTIONS on transactions
SP - 1948
EP - 1956
AU - Masakatsu NISHIGAKI
AU - Nobuyuki TANAKA
AU - Hideki ASAI
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1990
AB - In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.
ER -
English
