We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

This paper proposes the overlapped block relaxation Newton method for greatly reducing the number of iterations needed for simulating large scale nonlinear circuits. The circuit is partitioned into subcircuits, i.e., overlapped blocks consisting of core nodes and overlapped nodes. The core nodes form the core circuit for each overlapped block and the overlapped nodes form the overlapped circuit. The Newton-Raphson method is applied to all overlapped blocks independently and the approximation vector for relaxation is determined by node voltages of core nodes. An overlapped circuit is considered to be the representative circuit of the outside circuit for the core circuit. Therefore, the accuracy of the approximation vector for relaxation may be improved and the number of relaxation steps may be greatly reduced. Core nodes are determined automatically by reflecting the circuit structure, then the overlapping level is determined automatically. We show that this method has good performance for simulating large scale circuits, and that it is faster than the nonlinear direct method which is used in standard circuit simulators.

A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

This paper describes a mixed mode circuit simulation by the direct and relaxation-based methods with dynamic network partitioning. For the efficient circuit simulation by the direct method, the algorithms with circuit partitioning and latency technique have been studied. Recently, the hierarchical decomposition and latency and their validities have been researched. Network tearing techniques enable independent analysis of each subnetwork except for the local datum nodes. Therefore, if the local datum nodes are also torn, each subnetwork is separated entirely. Since the network separation is based on relaxation approach, the implementation of the separation technique in the circuit simulation by the direct method corresponds to performing the mixed mode simulation by the direct and relaxation-based methods. In this paper, a dynamic "network separation" technique based on the tightness of the coupling between subnetworks is suggested. Then, by the introduction of dynamic network separation into the simulator SPLIT with hierarchical decomposition and latency, the mixed mode circuit simulator, which selects the direct method or the relaxation method and determines the block size of the latent circuit dynamically and suitably, is constructed.

In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.

This letter describes the waveform relaxation method with local iteration and window partition techniques for the simulation of the circuit containing feedback loops. Finally, we apply this algorithm to the transient analysis of MOS circuits and verify its availability.

For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.

This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.

We have proposed parallel optical interconnection technology, or ParaBIT, for high-throughput, low-cost optical interconnections and already developed a prototype parallel optical interconnect module called "ParaBIT-0," which has a total throughput of 28 Gb/s (700 Mb/s 40 channels). We are now developing a compact, high-throughput module called "ParaBIT-1," which has a total throughput of 60 Gb/s (1.25 Gb/s 48 channels) and is designed to achieve the highest-ever throughput density of 3.3 Gb/s/cc. In this paper, we describe the packaging structure, optical coupling structure and transmission characteristics of ParaBIT-1. We also discuss the technical prospect of realizing a parallel optical interconnect module with the bit rate of 2.5 Gb/s/ch.

The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.

This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.