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[Author] Nobuaki MATSUURA(6hit)

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  • Experimental 5-Tb/s Packet-by-Packet Wavelength Switching System Using 2.5 -Gb/s 8-λ WDM Links

    Kimihiro YAMAKOSHI  Nobuaki MATSUURA  Kohei NAKAI  Eiji OKI  Naoaki YAMANAKA  Takaharu OHYAMA  Yuji AKAHORI  

     
    PAPER-Switching

      Vol:
    E85-B No:7
      Page(s):
    1293-1301

    We have developed an experimental 5-Tb/s packet-by-packet wavelength switching system, OPTIMA-2. This paper describes its hardware architecture. OPTIMA-2 is a non-blocking 3-stage switch using optical wavelength division multiplexing (WDM) links and dynamic bandwidth-sharing. A new scheduling algorithm for variable-length packets is used for the receiver ports of WDM links and simulation results show that it can suppress short-packet delay while keeping high throughput. An implementation of the WDM link using field programable gate arrays and a compact planar lightwave circuit platform is described. Experimental results for the basic operation of optical wavelength switching are also presented.

  • ParaBIT: Parallel Optical Interconnection for Large-Capacity ATM Switching Systems

    Kosuke KATSURA  Yasuhiro ANDO  Mitsuo USUI  Akira OHKI  Nobuo SATO  Nobuaki MATSUURA  Nobuyuki TANAKA  Toshiaki KAGAWA  Makoto HIKITA  

     
    INVITED PAPER-Assembly and Packaging Technologies

      Vol:
    E82-C No:2
      Page(s):
    360-369

    We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

  • Para BIT:Parallel Optical Interconnection for Large-Capacity ATM Switching Systems

    Kosuke KATSURA  Yasuhiro ANDO  Mitsuo USUI  Akira OHKI  Nobuo SATO  Nobuaki MATSUURA  Nobuyuki TANAKA  Toshiaki KAGAWA  Makoto HIKITA  

     
    INVITED PAPER-Assembly and Packaging Technologies

      Vol:
    E82-B No:2
      Page(s):
    412-421

    We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

  • Bidirectional Path Setup Scheme Using on Upstream Label Set in Optical GMPLS Networks

    Eiji OKI  Nobuaki MATSUURA  Kohei SHIOMOTO  Naoaki YAMANAKA  

     
    PAPER-Network

      Vol:
    E87-B No:6
      Page(s):
    1569-1576

    Generalized Multi-Protocol Label Switching (GMPLS) is being developed in the Internet Engineering Task Force (IETF). In GMPLS-based wavelength-division-multiplexing (WDM) optical networks, a wavelength in a fiber is used as a label. In the existing GMPLS signaling protocol for bidirectional paths in WDM networks with the wavelength continuity constraint, bidirectional path setup fails with high probability because the upstream label allocated by the previous hop node may not be accepted at the transit node. To solve this problem, this paper proposes an efficient bidirectional label switched path (LSP) setup scheme based on an upstream label set. Called the Upstream Label Set (ULS) scheme, it is an extension of the existing GMPLS signaling protocol. The ULS scheme is consistent with the existing GMPLS signaling procedure and so offers backward compatibility. The numerical results suggest that when the number of the LSP setup retries is limited, the ULS scheme offers lower blocking probability than the existing GMPLS signaling scheme which uses only with the upstream label (UL). In addition, under the condition that the constraint of the number of LSP setup retries is relaxed, the LSP setup time of the ULS scheme is faster than that of the existing scheme. Furthermore, by using our developed prototype of the GMPLS control system, in which the ULS scheme was installed, we demonstrated that the ULS scheme successfully setup bidirectional LSPs.

  • A Disjoint Path Selection Scheme with Shared Risk Link Group Constraints in GMPLS Networks

    Eiji OKI  Nobuaki MATSUURA  Kohei SHIOMOTO  Naoaki YAMANAKA  

     
    PAPER-Network

      Vol:
    E86-B No:8
      Page(s):
    2455-2462

    This paper proposes a disjoint path selection scheme for Generalized Multi-Protocol Label Switching (GMPLS) networks with Shared Risk Link Group (SRLG) constraints. It is called the weighted-SRLG (WSRLG) scheme. It treats the total number of SRLG members related to a link as part of the link cost when the k-shortest path algorithm is executed. In WSRLG, a link that has many SRLG members is rarely selected as the shortest path. Simulation results show that WSRLG finds more disjoint paths than the conventional k-shortest path algorithm. In addition, since WSRLG searches for the weight of the SRLG factor by using a modified binary search algorithm while satisfying the required number of disjoint paths between source and destination nodes, it can find cost-effective disjoint paths.

  • A Large-Scale IP and Lambda Integrated Router Architecture

    Michihiro AOKI  Miki HIRANO  Nobuaki MATSUURA  Takashi KURIMOTO  Takashi MIYAMURA  Masahiro GOSHIMA  Keisuke KABASHIMA  Shigeo URUSHIDANI  

     
    PAPER

      Vol:
    E86-B No:8
      Page(s):
    2302-2309

    The growth in the volume of Internet traffic and the increasing variety of Internet applications require Internet backbone networks to be scalable and provided sophisticated quality of service (QoS) capabilities. Internet backbone routers have evolved to achieve sub-Tbps switching capacity in a single unit, but their switch architectures have limited scalability, causing QoS to degrade as the switches get bigger. Hence, we propose a large-scale IP and lambda integrated router architecture with scalable switches. We first describe the system architecture of our proposed backbone router and clarify the requirements for its switching capabilities to meet near-future demands. The new switch architecture, using crossbar-based switching fabrics and optical interconnection devices, meets the requirements for a backbone router to scale up to 82 Tbps and enable light path switching as well as packet switching. The routing tag and its usage algorithm in the switch, and packaging issues, including the quantity of hardware required for expansion, are also discussed.