A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell, not arrival, allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

This letter presents SAM, a multiplexer for ATM's circuit emulation services that can precisely control the cell clumping at the connection-level. Compared with a FIFO (First In First Out) multiplexer, it also improves the connection-level diffusion and CDV (Cell Delay Variation) performance. SAM can therefore significantly increase the number of connections accepted by CAC (Call Admission Control) procedures in the subsequent multiplexer.

This letter proposes a VP-shaper for ATM networks that controls the VC-level cell clumping. The new shaper is compared with a conventional shaper and is found to significantly increase CAC (Call Admission Control) efficiency and achieve high VP utilization gain. Hardware implementation based on a shared buffer and chained lists is presented and its feasibility is shown.

In this paper, Transmission Control Protocol/Internet Protocol (TCP/IP) over Stream Control Transmission Protocol (SCTP)/IP parallel transmission system is proposed to realize large TCP/IP throughput. The proposed system enables SCTP/IP connection between switches by protocol stacking. The proposed system is implemented on a software switch to evaluate its performance. The evaluation result indicates that proposed system can achieve 90% throughput compared with serial transmission when the delay difference among parallel routes is 20 msec.

This paper presents two dynamic multi-layer routing policies for optical IP Networks. Both policies first try to allocate a newly requested electrical path to an existing optical path that directly connects the source and destination nodes. If such a path is not available, the two policies employ different procedures. Policy 1, which has been published already, tries to find available existing optical paths with two or more hops that connect the source and destination nodes. Policy 2, which is proposed in this paper, tries to establish a new one-hop optical path between source and destination nodes. The performances of the two routing policies are evaluated. Simulation results suggest that policy 2 outperforms policy 1 if p is large, where p is the number of packet-switching-capable ports; the reverse is true only if p is small. We observe that p is the key factor in choosing the most appropriate routing policy.

Information-centric networking (ICN) has been investigated as a new communication model that is optimal for data registration and retrieval. A promising application of ICN is mobile machine-to-machine (M2M) communication in which data are registered by M2M terminals, such as vehicles, and retrieved by other M2M terminals. One of the most difficult challenges with ICN is achieving data mobility in which the data are registered by moving terminals and the location of the data changes constantly. To gain access to moving data, the data retrieval messages must access the routing information, which results in a high volume of message transaction loads of high-tier nodes such as the name resolution nodes. We previously proposed a scheme called data-centric network (DCN), which mitigates this problem by allocating multiple intermediate nodes that act as route aggregation points and by establishing optimized routes. In this paper, we compare the transaction load of DCN with those of conventional ICN schemes using theoretical evaluation based on probability calculation. We also compare the amount of route information and transaction loads using a simulator against binary tree and ISP backbone topologies. From these evaluations, we clarify the characteristics of each ICN scheme in different terminal distribution and communication patterns and show that DCN reduces the transaction loads of high-tier nodes when the terminals are communicating locally.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

The benefits of ATM techniques have been widely recognized and many organizations envisage the introduction of ATM techniques into their telecommunication networks. The ATM benefits can, however, be fully exploited only after effective network resource management techniques have been developed. This paper focuses on CBR-VP management techniques. The ATM transport network architecture and VP roles are summarized. Next, the issues of VP accommodation design are described. The point is how to create a design that accommodates cell loss and cell delay jitter, both of which depend on various network parameters and conditions. For this purpose, analytical procedures based on an M/D/1 queueing model are adopted. The approximation method is shown to be very effective in practical use through computer analysis. The method guarantees conservative QOSs. Finally, the proposed method is applied to several design examples to illustrate VP management issues. The proposed method will enable ATM techniques to be introduced to our telecommunication networks by the mid-1990's.

This letter proposes a new UPC (Usage Parameter Control) method suitable for monitoring/controlling the ATM cell streams of VCs (Virtual Channels) and VPs (Virtual Paths) specified with a wide-range of traffic parameter values. The method, named the 2-phase T-X method, combines two credit window type monitoring circuits that are shifted in phase by T/2. The proposed method achieves the best of both the DB and T-X methods. Its cell mis-policing rate is very low (equivalent to that of the DB-method) while its minimal hardware requirements are equal to those of the T-X method. The proposed method ensures more effective network resource (link) utilization. As a result, the proposed method is shown to be a credible UPC technique for handling broadband VBR (Variable Bit Rate) traffic in ATM based multimedia networks.

The first global interoperability experiment of GMPLS controlled Ethernet with VLAN tag swapping between two different implementations is successfully demonstrated. High definition video streaming is realized through a newly established Layer 2 Label Switched Path (L2-LSP). The results of this experiment can be applied to designing reliable Layer 2 networks.

We have developed an experimental 5-Tb/s packet-by-packet wavelength switching system, OPTIMA-2. This paper describes its hardware architecture. OPTIMA-2 is a non-blocking 3-stage switch using optical wavelength division multiplexing (WDM) links and dynamic bandwidth-sharing. A new scheduling algorithm for variable-length packets is used for the receiver ports of WDM links and simulation results show that it can suppress short-packet delay while keeping high throughput. An implementation of the WDM link using field programable gate arrays and a compact planar lightwave circuit platform is described. Experimental results for the basic operation of optical wavelength switching are also presented.

A multicast ATM switch with a new external copy module is proposed. The copy module, called copy-trunk, has two new functions to guarantee the QoS of P-MP cells: The delay priority control function and the output-cell-spacing control function. By using the delay priority control function, copied cells with high-priority are always released earlier than those with low-priority so as to avoid increasing the delay time of real-time traffic. The output-cell-spacing control function is used to reduce the burstiness of the output traffic. The output pattern is adaptively controlled by measuring the input load. The effects of these two controls are quantitatively described. The copy-trunk allows the multicast capability of a switch to be efficiently and economically increased to satisfy future traffic volume and services.

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed -Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture,and will be suitable for future high-speed multimedia ATM networks.

This letter studies the Peak Cell Rate (PCR) policing of ATM connections that consist of multiple cell flow components. It is shown that the conventional methods proposed for policing the aggregate flow do not use the network's resources efficiently. This letter proposes a simple and efficient UPC (Usage Parameter Control) mechanism based on a tandem leaky bucket for multi-component ATM connections. The results show that network resource requirements can be minimized, with reasonable hardware complexity.

This letter proposes ALPEN, a simple, flexible and cost effective ATM-WAN architecture that emulates multiple ATM-layer protocols at the edge nodes. Any new ATM-layer protocol can be easily implemented by modifying only the edge nodes. The transit network is simple and independent of the protocols emulated, and ALPEN has a short response time. It is very suitable for implementing multimedia ATM networks.

We propose a buffer management mechanism, called V-WFQ (Virtual Weighted Fair Queueing), for achieving an approximately fair allocation of bandwidth with a small amount of hardware in a high-speed network. The basic process for the allocation of bandwidth uses selective packet dropping that compares the measured input rate of the flow with an estimated fair share of bandwidth. Although V-WFQ is a hardware-efficient FIFO-based algorithm, it achieves almost ideal fairness in bandwidth allocation. V-WFQ can be implemented in the high-speed core routers of today's IP backbone networks to provide various high-quality services. We have investigated V-WFQ's performance in terms of fairness and link utilization through extensive simulation. The results of simulation show that V-WFQ achieves a good balance between fairness and link utilization under various simulation conditions.