A three-stage Clos-network switch with input queues is attractive for practical implementation of a large-capacity packet switch. A scheme that configures the first, second, and third stages in that sequence by performing iterative matchings based on random selections is called the staged random scheduling scheme. Despite the usefulness of such a switch, the literature provides no analytical formula that can accurately calculate its throughput. This paper develops a formula to calculate the throughput analysis of the staged random scheduling scheme for one and multiple iterations used in an input-queued Clos-network switch under uniform traffic. This formula can be used to verify simulation models for very large switches. The introduced derivation considers the processes of the selection scheme at each stage of the switch. The derived formula is used in numerical evaluations to show the throughput of large switch sizes. The results show that the staged random scheduling scheme with multiple iterations for a Clos-network switch with VOQs without internal expansion approaches 100% throughput under uniform traffic. Furthermore, evaluations of the derived formulas are used in a practical application to estimate the number of iterations required to achieve 99% throughput for a given switch size. In addition, the staged random scheduling scheme in an input-queued Clos-network switch is modeled and simulated to compare throughput estimations to those obtained with the derived formulas. The simulation results support the correctness of the derived formulas.

This paper proposes a Generalized Traffic Engineering Protocol (GTEP). GTEP is a protocol that permits communication between a Path Computation Element (PCE) and a Generalized Multi-Protocol Label Switching (GMPLS) controller (CNTL). The latter is hosted by each GMPLS node; it handles GMPLS and MPLS protocols such as routing and signaling protocols as well as controlling the GMPLS node host. The PCE provides multi-layer traffic engineering; it calculates Label Switched Path (LSP) routes and judges whether a new lower-layer LSP should be established. GTEP functions are implemented in both the PCE and GMPLS router. We demonstrate a multi-layer traffic engineering experiment conducted with GTEP.

This letter presents the optimal routing by the intermediate model; a construction that lies between the pipe and hose models. We show that it is a practical way of realizing optimal routing. A formulation extended from the pipe model to the intermediate model can not be solved as a regular linear programming (LP) problem. Our solution, the introduction of a duality theorem, successfully turns our problem into an LP formulation that can be easily solved. Numerical results show that the intermediate model has better routing performance than the hose model.

The performance of packet processing applications is dependent on the memory access speed of network systems. Table lookup requires fast memory access and is one of the most common processes in various packet processing applications, which can be a dominant performance bottleneck. Therefore, in Network Function Virtualization (NFV)-aware environments, on-chip fast cache memories of a CPU of general-purpose hardware become critical to achieve high performance packet processing speeds of over tens of Gbps. Also, multiple types of applications and complex applications are executed in the same system simultaneously in carrier network systems, which require adequate cache memory capacities as well. In this paper, we propose a packet processing architecture that utilizes interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices as off-chip Last Level Cache (LLC) in addition to several levels of dedicated cache memories of each CPU core. Entries of a lookup table are distributed in every bank and vault to utilize both bank interleaving and vault-level memory parallelism. Frequently accessed entries in 3D-stacked DRAM are also cached in on-chip dedicated cache memories of each CPU core. The evaluation results show that the proposed architecture reduces the memory access latency by 57%, and increases the throughput by 100% while reducing the blocking probability but about 10% compared to the architecture with shared on-chip LLC. These results indicate that 3D-stacked DRAM can be practical as off-chip LLC in parallel packet processing systems.

This paper proposes a multiple QoS control scheme that combines the head-of-line priority (HOLP) discipline with equivalent-window connection admission control (CAC). The proposed scheme can support the different cell loss ratios of both delay-sensitive traffic in high-priority buffers and delay-tolerant traffic in low-priority buffers. The CAC scheme extends a measurement-based CAC algorithm for a single buffer to the low-priority buffer with the HOLP discipline to provide the cell loss ratio objective. We introduce an equivalent window for monitoring low-priority cell streams. The equivalent window size equals the period within which the number of times the low-priority buffer is scanned to read cells is constant. Thus the equivalent window size varies with the high-priority queueing state. Numerical results indicate that the proposed QoS control scheme using the equivalent-window CAC can utilize network resources more effectively than the conventional control scheme which is Virtual Path (VP) separation for different cell loss requirement services. In addition, it is confirmed that the proposed scheme provides conservative admissible loads. Thus, this proposed scheme can achieve large statistical gains while providing both high-priority and low-priority cell loss ratio objectives. The proposed scheme will be very useful for cost-effective multimedia services that have different QoS requirements.

An experimental 640-Gbit/s ATM switching system is described. The switching system is scalable and quasi-non-blocking and uses hardware self-rearrangement in a three-stage network. Hardware implementation results for the switching system are presented. The switching system is fabricated using advanced 0.25-µm CMOS devices, high-density multi-chip-module (MCM) technology, and optical wavelength-division-multiplexing (WDM) interconnection technology. A scalable 80-Gbit/s switching module is fabricated in combination with a developed scalable-distributed-arbitration technique, and a WDM interconnection system that connects multiple 80-Gbit/s switching modules is developed. Using these components, an experimental 640-Gbit/s switching system is partially constructed. The 640-Gbit/s switching system will be applied to future broadband ATM networks.

This letter presents a theoretical analysis of the Parallel Iterative Matching (PIM)'s dynamics with multiple iterations used in an input-buffered packet switch. In our approach, by carefully categorizing all unmatched patterns into several representative patterns after each iteration, probabilities of accumulated matched pairs in a recursive manner are successfully obtained. Numerical evaluations of the analytical formulas are performed.

This paper proposes an optimization model under uncertain traffic demands to design the backup network to minimize the total capacity of a backup network to protect the primary network from multiple link failures, where the probability of link failure is specified. The hose uncertainty is adopted to express uncertain traffic demands. The probabilistic survivability guarantee is provided by determining both primary and backup network routing, simultaneously. Robust optimization is introduced to provide probabilistic survivability guarantees for different link capacities in the primary network model under the hose uncertainty. Robust optimization in the proposed model handles two uncertain items: uncertain failed primary link with different capacities and uncertain traffic demands. We formulate an optimization problem for the proposed model. Since it is difficult to directly solve it, we introduce a heuristic approach for the proposed model. By using the heuristic approach, we investigate how the probability of link failure affects both primary and backup network routing. Numerical results show that the proposed model yields a backup network with lower total capacity requirements than the conventional model for the link failure probabilities examined in this paper. The results indicate that the proposed model reduces the total capacity of the backup network compared to the conventional model under the hose uncertainty. The proposed model shares more effectively the backup resources to protect primary links by determining routing in both primary and backup networks.

This paper proposes an optimization approach that designs the backup network with the minimum total capacity to protect the primary network from random multiple link failures with link failure probability. In the conventional approach, the routing in the primary network is not considered as a factor in minimizing the total capacity of the backup network. Considering primary routing as a variable when deciding the backup network can reduce the total capacity in the backup network compared to the conventional approach. The optimization problem examined here employs robust optimization to provide probabilistic survivability guarantees for different link capacities in the primary network. The proposed approach formulates the optimization problem as a mixed integer linear programming (MILP) problem with robust optimization. A heuristic implementation is introduced for the proposed approach as the MILP problem cannot be solved in practical time when the network size increases. Numerical results show that the proposed approach can achieve lower total capacity in the backup network than the conventional approach.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

This paper presents a high-speed CAC scheme, called PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating virtual requests for connection. When an actual new request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth. PERB CAC provides very rapid response time both for statistical and deterministic bandwidth allocation services, while keeping statistical multiplexing gain for the former service. Numerical results indicate that PERB CAC provides reasonably accurate and conservative values of residual bandwidth. In addition, by using PERB CAC, both services are able to be accommodated into a single VP. VP capacity control is more relaxed than is true with conventional VP-separation management. This is another merit of PERB CAC. Therefore, PERB CAC can achieve high-speed connection set-up while utilizing network resources in a cost-effective manner.

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

This paper describes a distributed traffic control scheme for large multi-stage ATM switching systems. When a new virtual circuit is to be added from some source line-interface unit (LU) to a destination LU, the system must find an optimal path through the system to accommodate the new circuit. Conventional systems have a central control processor and control lines to manage the bandwidth of all the links in the systems. The central control processor handles all the virtual circuits, but have trouble doing this when the switching system becomes large because of the limited ability of the central processor to handle the number of virtual circuits. A large switching system with Tbit/s-class throughput requires a distributed traffic control scheme. In our proposed switching system, each port of the basic switches has its own traffic monitor. Operation, administration, and maintenance (OAM) cells that are defined inside the system carry the path-congestion information to the LUs, enabling each LU to route new virtual circuits independently. A central control processor and control lines are not required. The performance of the proposed system depends on the interval between OAM cells. This paper shows how an optimal interval can be determined in order to maximize the bandwidth for user cells. This traffic control scheme will suit future Tbit/s ATM switching systems.

The Machine-to-Machine (M2M) service network platform accommodates M2M communications traffic efficiently by using tree-structured networks and the computation resources deployed on network nodes. In the M2M service network platform, program files required for controlling devices are placed on network nodes, which have different amounts of computation resources according to their position in the hierarchy. The program files must be dynamically repositioned in response to service quality requests from each device, such as computation power, link bandwidth, and latency. This paper proposes a Program File Placement (PFP) method for the M2M service network platform. First, the PFP problem is formulated in the Mixed-Integer Linear Programming (MILP) approach. We prove that the decision version of the PFP problem is NP-complete. Next, we present heuristic algorithms that attain sub-optimal but attractive solutions. Evaluations show that the heuristic algorithm based on the number of devices that share a program file reduces the total number of placed program files compared to the algorithm that moves program files based on their position.

The scalability of three-stage Clos-network packet switches makes them an attractive approach in implementing large-size packet switches. However, the configuration time of Clos-network switches depends on both the buffering strategy used and the adopted configuration process. To reduce configuration time, this paper focuses on the so-called Memory-Space-Memory (MSM) Clos-network packet switch, where the switch modules in the first and third stages use memory to support resolution of output port contention. The configuration of these switches is then based on a process to dispatch cells from the first-stage modules to the third-stage modules. Therefore, the throughput of an MSM Clos-network switch depends on the dispatching scheme used. This paper introduces a cell dispatching scheme, called maximum weight matching dispatching (MWMD) scheme, for MSM Clos-network switches and a request queue structure in the first-stage modules. The MWMD scheme performs maximum weight matching, similar to that used for input-queued single-stage packet switches, that in combination with the request queues can achieve 100% throughput under independent and identical admissible traffic. This high throughput can be achieved without allocating buffers in the second stage and without expanding the second stage of this three-stage packet switch. A low-complexity dispatching scheme, the maximal oldest-cell-first matching dispatching (MOMD) scheme, is also introduced as an alternative to MWMD. The performance evaluation in this paper shows that MOMD achieves high throughput under unbalanced traffic through the execution of a finite number of iterations.

The Internet is an extremely convenient network and has become one of the key infrastructures for daily life. However, it suffers from three serious problems; its structure does not suit traffic centralization, its power consumption is rapidly increasing, and its round-trip time (RTT) and delay jitter are large. This paper proposes an extremely energy efficient layer-3 network architecture for the future Internet. It combines the Service Cloud with the Cloud Router and application servers, with the Optical Aggregation Network realized by optical circuit switches, wavelength-converters, and wavelength-multiplexers/demultiplexers. User IP packets are aggregated and transferred through the Optical Aggregation Network to Cloud transparently. The proposed network scheme realizes a network structure well suited to traffic centralization, reduces the power consumption to 1/20-1/30 compared to the existing Internet, reduces the RTT and delay jitter due to its simplicity, and offers easy migration from the existing Internet.

This paper proposes an efficient server selection scheme in successive participation scenario with participating-domain segmentation. The scheme is utilized by distributed processing systems for real-time interactive communication to suppress the communication latency of a wide-area network. In the proposed scheme, users participate for server selection one after another. The proposed scheme determines a recommended server, and a new user selects the recommended server first. Before each user participates, the recommended servers are determined assuming that users exist in the considered regions. A recommended server is determined for each divided region to minimize the latency. The new user selects the recommended available server, where the user is located. We formulate an integer linear programming problem to determine the recommended servers. Numerical results indicate that, at the cost additional computation, the proposed scheme offers smaller latency than the conventional scheme. We investigate different policies to divide the users' participation for the recommended server finding process in the proposed scheme.

This letter proposes a scalable network emulator architecture to support IP optical network management. The network emulator uses the same router interfaces to communicate with the IP optical TE server as the actual IP optical network, and behaves as an actual IP optical network between the interfaces. The network emulator mainly consists of databases and three modules: interface module, resource simulator module, and traffic generator module. To make the network emulator scalable in terms of network size, we employ TCP/IP socket communications between the modules. The proposed network emulator has the benefit that its implementation is not strongly dependent on hardware limitations. We develop a prototype of the network emulator based on the proposed architecture. Our design and experiments show that the proposed architecture is effective.

In 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) systems, when HARQ (Hybrid Automatic Repeat request) retransmission is invoked, the data at the transmitter are retransmitted randomly or sequentially regardless of their relationship to the wrongly decoded data. Such practice is inefficient since precious transmission resources will be spent to retransmit data that may be of no use in error correction at the receiver. This paper proposes an incremental redundancy HARQ scheme based on Error Position Estimating Coding (ePec) and LDPC (Low Density Parity Check Code) channel coding, which is called ePec-LDPC HARQ. The proposal is able to feedback the wrongly decoded code blocks within a specific MAC (Media Access Control) PDU (Protocol Data Unit) from the receiver. The transmitter gets the feedback information and then performs targeted retransmission. That is, only the data related to the wrongly decoded code blocks are retransmitted, which can improve the retransmission efficiency and thus reduce the retransmission overload. An enhanced incremental redundancy LDPC coding approach, called EIR-LDPC, together with a physical layer framing method, is developed to implement ePec-LDPC HARQ. Performance evaluations show that ePec-LDPC HARQ reduces the overall transmission resources by 15% compared to a conventional LDPC HARQ scheme. Moreover, the average retransmission times of each MAC PDU and the transmission delay are also reduced considerably.