IEICE TRANSACTIONS on Electronics
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip
Summary :
A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E98-C No.1 pp.45-52
- Publication Date
- 2015/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E98.C.45
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Naoki MIURA
Nippon Telegraph and Telephone Corporation (NTT)
Akihiko MIYAZAKI
Nippon Telegraph and Telephone Corporation (NTT)
Junichi KATO
Nippon Telegraph and Telephone Corporation (NTT)
Nobuyuki TANAKA
Nippon Telegraph and Telephone Corporation (NTT)
Satoshi SHIGEMATSU
Nippon Telegraph and Telephone Corporation (NTT)
Masami URANO
NTT Electronics Corporation
Mamoru NAKANISHI
NTT Electronics Corporation
Tsugumichi SHIBATA
Nippon Telegraph and Telephone Corporation (NTT)
Keyword
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Naoki MIURA, Akihiko MIYAZAKI, Junichi KATO, Nobuyuki TANAKA, Satoshi SHIGEMATSU, Masami URANO, Mamoru NAKANISHI, Tsugumichi SHIBATA, "Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip" in IEICE TRANSACTIONS on Electronics,
vol. E98-C, no. 1, pp. 45-52, January 2015, doi: 10.1587/transele.E98.C.45.
Abstract: A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.45/_p
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@ARTICLE{e98-c_1_45,
author={Naoki MIURA, Akihiko MIYAZAKI, Junichi KATO, Nobuyuki TANAKA, Satoshi SHIGEMATSU, Masami URANO, Mamoru NAKANISHI, Tsugumichi SHIBATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip},
year={2015},
volume={E98-C},
number={1},
pages={45-52},
abstract={A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.},
keywords={},
doi={10.1587/transele.E98.C.45},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip
T2 - IEICE TRANSACTIONS on Electronics
SP - 45
EP - 52
AU - Naoki MIURA
AU - Akihiko MIYAZAKI
AU - Junichi KATO
AU - Nobuyuki TANAKA
AU - Satoshi SHIGEMATSU
AU - Masami URANO
AU - Mamoru NAKANISHI
AU - Tsugumichi SHIBATA
PY - 2015
DO - 10.1587/transele.E98.C.45
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2015
AB - A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.
ER -
English
