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[Author] Junichi KATO(2hit)

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  • A Design Method for Logical Topologies with Stable Packet Routing in IP over WDM Network

    Junichi KATOU  Shin'ichi ARAKAWA  Masayuki MURATA  

     
    PAPER

      Vol:
    E86-B No:8
      Page(s):
    2350-2357

    An IP (Internet Protocol) over WDM network is expected to be an infrastructure for the next-generation Internet by directly carrying IP packets on the WDM-based network. Among several architectures for IP over WDM networks, one promising way is to overlay a logical topology consisting of lightpaths over the physical WDM network so that IP packets are carried on the lightpaths. The conventional methods for designing the logical topology have been focusing on maximizing throughput of the traffic. However, when the WDM network is applied to IP, the end-to-end path provided by the logical topology of the WDM network is not suitable to IP since IP has its own metrics for route selection. In this paper, we propose a new heuristic algorithm to design a logical topology by considering the delay between nodes as an objective metric. This algorithm uses a non-bifurcated flow deviation to obtain a set of routes that IP packets are expected to traverse. Our proposal is then compared with conventional methods in terms of the average packet delays and throughput. It is shown that our method becomes effective when the number of wavelengths is a limited resource.

  • Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip

    Naoki MIURA  Akihiko MIYAZAKI  Junichi KATO  Nobuyuki TANAKA  Satoshi SHIGEMATSU  Masami URANO  Mamoru NAKANISHI  Tsugumichi SHIBATA  

     
    PAPER-Electronic Circuits

      Vol:
    E98-C No:1
      Page(s):
    45-52

    A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.