In the circuit simulation by the direct method, it is a very important problem how to solve efficiently large scale sparse linear equations. For this problem, several network tearing techniques have been studied. This paper describes an automatic system for hierarchical decomposition of a large scale network. This system has a graphic circuit editor GRACE. GRACE enables to input a large scale circuit hierarchically, and to translate inputted circuit diagrams automatically into the hierarchical structural description language HAL. Furthemore, this system partitions the circuit hierarchically into gate level circuits, utilizing the HAL netlist. In this research, first we discuss the hierarchical tearing algorithm for large scale integrated circuits. Finally, we apply this system to TTL networks, and verify its availability by estimating the amount of computations required for triangular factorization of circuit matrices.

This report describes face image recognition by 2-dimensional discrete Walsh transform and multi-layer neural networks. Neural network (NN) is one of the powerful tools for pattern recognition. In the previous researches of face image recognition by NN, the gray levels on each pixel of the face image have been used for input data to NN. However, because the face image has usually too many pixels, a variety of approaches have been required to reduce the number of the input data. In this research, 2-dimensional discrete Walsh transform is used for reduction of input data and the recognition is done by multi-layer neural networks. Finally, the validity of our method is varified.

Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.

For stable solution of a linear equation, the modified relaxation-based algorithms have been proposed in both fields of circuit simulation and digital signal processing. This letter describes the analogy between these modified iterative methods proposed independently in two fields.

This letter describes the waveform relaxation method with local iteration and window partition techniques for the simulation of the circuit containing feedback loops. Finally, we apply this algorithm to the transient analysis of MOS circuits and verify its availability.

This letter describes the relaxation-based circuit simulation in the frequency domain. First, we present Iterated Spectrum Analysis, where the harmonic balance method is applied to each node. Furthermore, we refer to frequency domain latency and verify its availability for spectrum analysis.

This paper describes the expanded generalized method of characteristics (GMC) in order to handle large linear interconnect networks. The conventional GMC is applied to modeling each of transmission lines. Therefore, this method is not suitable to deal with large linear networks containing many transmission lines. Here, we propose the expanded GMC method to overcome this problem. This method computes a characteristic impedance and a new propagation function of the large linear networks containing many transmission lines. Furthermore the wave propagation delay is removed from the new wave propagation function using delay evaluation technique. Finally, it is shown that the present method enables the efficient and accurate simulation of the transmission line networks.

This paper describes an efficient simulator for state transition analysis of multivalued continuous-time neural networks, where the multivalued transfer function of neuron is regarded as a stepwise constant one. Use of stepwise constant method enables to analyse the state transition of the network without solving explicitly the differential equations. This method also enables to select the optimal timestep in numerical integration. The proposed method is implemented on the simulator and applied to the general neural network analysis. Furthermore, this is compared with the conventional simulators. Finally, it is shown that our simulator is drastically faster and more practical than the conventional simulators.

This paper presents the selective orthogonal matrix least-squares (SOM-LS) method for representing a multiport network characterized by sampled data with the rational matrix, improving the previous works, and providing new criteria. Recently, it is needed in a circuit design to evaluate physical effects of interconnects and package, and the evaluation is done by numerical electromagnetic analysis or measurement by network analyzer. Here, the SOM-LS method with the criteria will play an important role for generating the macromodels of interconnects and package in circuit simulation level. The accuracy of the macromodels is predictable and controllable, that is, the SOM-LS method fits the rational matrix to the sampled data, selecting the dominant poles of the rational matrix. In examples, simple PCB models are analyzed, where the rational matrices are described by Verilog-A, and some simulations are carried out on a commercial circuit simulator.

A new algorithm, which is incorporated into the waveform relaxation analysis, for efficiently simulating the transient response of single lossy transmission lines or lossy coupled multiconductor transmission lines, terminated with arbitrary networks will be presented. This method exploits the inherent delay present in a transmission line for achieving simulation efficiency equivalent to obtaining converged waveforms with a single iteration by the conventional iterative waveform relaxation approach. To this end we propose 'line delay window partitioning' algorithm in which the simulation interval is divided into sequential windows of duration equal to the transmission line delay. This window scheme enables the computation of the reflected voltage waveforms accurately, ahead of simulation, in each window. It should be noted that the present window partitioning scheme is different from the existing window techniques which are aimed at exploiting the non–uniform convergence in different windows. In contrast, the present window technique is equivalent to achieving uniform convergence in all the windows with a single iteration. In addition our method eliminates the need to simulate the transmission line delay by the application of Branin's classical method of characteristics. Further, we describe a simple and efficient method to compute the attenuated waveforms using a particular form of lumped element model of attenuation function. Simulation examples of both single and coupled lines terminated with linear and nonlinear elements will be presented. Comparison indicates that the present method is several times faster than the previous waveform relaxation method and its accuracy is verified by the circuit simulator PSpice.

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.

This paper describes an efficient method to simulate lossy coupled transmission lines based on the delay evaluation technique. First, we review the previous methods, and refer to several problems concerned with these methods. Next, a novel waveform relaxation-based simulation method is proposed, which uses the delay evaluation technique. This method enables to obtain the accurate transient waveforms using smaller number of moments than the other moment methods use, and is modified for acceleration by the generalized line delay window partitioning (GLDW) technique. Finally, this method is implemented in the waveform relaxation-based circuit simulator DESIRE3T+, and the performance is estimated.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) cylindric puzzles which are problems to arrange the irregular-shaped slices so that they perfectly fit into a fixed three dimensional cylindric shape. First, the idea to expand the 2-dimensional tiling technique to 3-dimensional puzzles is described. Next, to energy function with the fitting function of each polyomino is introduced, which is available for 3-D cylindric puzzles. Furthermore our algorithm is applied to several examples using the analog neural array. Finally, it is shown that our algorithm is useful for solving 3-D cylindric puzzles.

This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.

A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

In this paper, we propose a floating resistor circuit with positive and negative resistance operating at the low supply voltages 1.5 V. Only two transistors are connected between supply lines in order to operate under the low power supply voltages. In this circuit, current subtraction is carried out at the gate terminal for which input/output voltage is applied. As a result, the proposed circuit can realize the large range of resistance of positive and negative resistances. Therefore, in an application, the proposed circuit is used in neuro-based limit cycle generator as synaptic weights.

The conventional synthesis procedure of discrete time sparsely interconnected neural networks (DTSINNs) for associative memories may generate the cells with only self-feedback due to the sparsely interconnected structure. Although this problem is solved by increasing the number of interconnections, hardware implementation becomes very difficult. In this letter, we propose the DTSINN system which stores the 2-dimensional discrete Walsh transforms (DWTs) of memory patterns. As each element of DWT involves the information of whole sample data, our system can associate the desired memory patterns, which the conventional DTSINN fails to do.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.