A parallel detailed router based on the area division is one of important tools to overcome the increase of CPU time required for routing of a very large multilayer SOG. In order to conduct routing in each divided area independently, fictitious terminals are introduced on the border of each divided area, and routes connected to the fictitious terminals are concatenated to complete the final detailed routes. In this paper, we consider a problem how to position such fictitious terminals on borders, so as to make each detailed routing in a divided area easy. We formulate this problem as a minimum cost assignment problem, and propose an iterative improvement algorithm. We also give some experimental results which indicate the effectiveness of the algorithm.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.

This paper describes an efficient simulation algorithm for the spatiotemporal pattern analysis of the continuous-time neural networks with the multivalued logic (multivalued continuous-time neural networks). The multivalued transfer function of neuron is approximated to the stepwise constant function which is constructed by the sum of the step functions with the different thresholds. By this approximation, the dynamics of the network can be formulated as a stepwise constant linear differential equation at each timestep and the optimal timestep for the numerical integration can be obtained analytically. Finally, it is shown that the proposed method is much faster than a variety of conventional simulators.

This paper describes the expanded generalized method of characteristics (GMC) in order to handle large linear interconnect networks. The conventional GMC is applied to modeling each of transmission lines. Therefore, this method is not suitable to deal with large linear networks containing many transmission lines. Here, we propose the expanded GMC method to overcome this problem. This method computes a characteristic impedance and a new propagation function of the large linear networks containing many transmission lines. Furthermore the wave propagation delay is removed from the new wave propagation function using delay evaluation technique. Finally, it is shown that the present method enables the efficient and accurate simulation of the transmission line networks.

This paper describes an efficient simulator for state transition analysis of multivalued continuous-time neural networks, where the multivalued transfer function of neuron is regarded as a stepwise constant one. Use of stepwise constant method enables to analyse the state transition of the network without solving explicitly the differential equations. This method also enables to select the optimal timestep in numerical integration. The proposed method is implemented on the simulator and applied to the general neural network analysis. Furthermore, this is compared with the conventional simulators. Finally, it is shown that our simulator is drastically faster and more practical than the conventional simulators.

This paper describes an efficient method to simulate lossy coupled transmission lines based on the delay evaluation technique. First, we review the previous methods, and refer to several problems concerned with these methods. Next, a novel waveform relaxation-based simulation method is proposed, which uses the delay evaluation technique. This method enables to obtain the accurate transient waveforms using smaller number of moments than the other moment methods use, and is modified for acceleration by the generalized line delay window partitioning (GLDW) technique. Finally, this method is implemented in the waveform relaxation-based circuit simulator DESIRE3T+, and the performance is estimated.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.

With the progress of integration of circuits and PCBs (Printed Circuit Boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain the interconnects with nonlinear terminations. This simulator is based on the environmental tool ASSIST (Assistant System for Simulation Study) constructed for development of the circuit simulators, and is combined with PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm). In this simulator, an efficient implementation of PRIMA is considered with using a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of the simple PCBs, and the validity is verified.

In this paper, we propose a new method which makes transient simulation faster for the circuit including both nonlinear and linear elements. First, the method for generating the projection matrix with Krylov-subspace technique is described. The order of the circuit equation is reduced by congruence transformation with the projection matrix. Next, we suggest a method which can calculate the reduced Jacobian matrix directly in each Newton-Raphson iteration. Since this technique does not need to calculate the original size of Jacobian matrix, the calculation cost is reduced drastically. Therefore, efficient circuit simulation can be achieved. Finally, our method is applied to some example circuits and the validity of the nonlinear circuit reduction technique is verified.