IEICE TRANSACTIONS on transactions
Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method
Summary :
Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E71-E No.10 pp.962-964
- Publication Date
- 1988/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Numerical Calculation and Mathematical Programming
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hideki ASAI, Atsushi KUMITA, "Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method" in IEICE TRANSACTIONS on transactions,
vol. E71-E, no. 10, pp. 962-964, October 1988, doi: .
Abstract: Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e71-e_10_962/_p
Copy
@ARTICLE{e71-e_10_962,
author={Hideki ASAI, Atsushi KUMITA, },
journal={IEICE TRANSACTIONS on transactions},
title={Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method},
year={1988},
volume={E71-E},
number={10},
pages={962-964},
abstract={Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method
T2 - IEICE TRANSACTIONS on transactions
SP - 962
EP - 964
AU - Hideki ASAI
AU - Atsushi KUMITA
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 10
JA - IEICE TRANSACTIONS on transactions
Y1 - October 1988
AB - Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.
ER -
English
