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[Author] Masahiro YOSHIDA(8hit)

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  • Caching-Based Multi-Swarm Collaboration for Improving Content Availability in BitTorrent

    HyunYong LEE  Masahiro YOSHIDA  Akihiro NAKAO  

     
    PAPER-Information Network

      Vol:
    E95-D No:5
      Page(s):
    1446-1453

    Despite its great success, BitTorrent suffers from the content unavailability problem where peers cannot complete their content downloads due to some missing chunks, which is caused by a shortage of seeders who hold the content in its entirety. The multi-swarm collaboration approach is a natural choice for improving content availability, since content unavailability cannot be overcome by one swarm easily. Most existing multi-swarm collaboration approaches, however, suffer from content-related limitations, which limit their application scopes. In this paper, we introduce a new kind of multi-swarm collaboration utilizing a swarm as temporal storage. In a nutshell, the collaborating swarms cache some chunks of each other that are likely to be unavailable before the content unavailability happens and share the cached chunks when the content unavailability happens. Our approach enables any swarms to collaborate with each other without the content-related limitations. Simulation results show that our approach increases the number of download completions by over 50% (26%) compared to normal BitTorrent (existing bundling approach) with low overhead. In addition, our approach shows around 30% improved download completion time compared to the existing bundling approach. The results also show that our approach enables the peers participating in our approach to enjoy better performance than other peers, which can be a peer incentive.

  • New Bias Voltage Generators for TFT-LCD's Drivers

    Manabu HIRATA  Yasoji SUZUKI  Masahiro YOSHIDA  Yutaka ARAYASHIKI  Mitsuo TERAMOTO  Somsak CHOOMCHUAY  

     
    PAPER

      Vol:
    E83-C No:10
      Page(s):
    1579-1583

    New positive and negative bias voltage generators for TFT-LCD's drivers utilizing charge pump circuits are introduced. The generators can generate positive or negative voltages with various amplitude by simply changing the number of pumping stages. By using the circuit simulation program HSPICE, it is demonstrated that the introduced generators can provide enough positive or negative voltages for TFT-LCD's drivers.

  • Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network

    Masahiro YOSHIDA  Takeshi KAMIO  Hideki ASAI  

     
    LETTER-Source Coding/Image Processing

      Vol:
    E86-A No:10
      Page(s):
    2623-2627

    This report describes face image recognition by 2-dimensional discrete Walsh transform and multi-layer neural networks. Neural network (NN) is one of the powerful tools for pattern recognition. In the previous researches of face image recognition by NN, the gray levels on each pixel of the face image have been used for input data to NN. However, because the face image has usually too many pixels, a variety of approaches have been required to reduce the number of the input data. In this research, 2-dimensional discrete Walsh transform is used for reduction of input data and the recognition is done by multi-layer neural networks. Finally, the validity of our method is varified.

  • Simultaneous Approximation for Magnitude and Phase Responses of FIR Digital Filters

    Masahiro OKUDA  Masahiro YOSHIDA  Masaaki IKEHARA  Shin-ichi TAKAHASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E87-A No:11
      Page(s):
    2957-2963

    In this paper, we present a new numerical method for the complex approximation of FIR digital filters. Our objective is to design FIR filters with equiripple magnitude and phase errors. The proposed method solves the least squares (LS) problem iteratively. At each iteration, the desired response is updated so as to have an equiripple error. The proposed methods do not require any time-consuming optimization procedure such as the quasi-Newton methods and converge to equiripple solutions quickly. We show some examples to illustrate the advantages of our proposed methods.

  • Edge Computing-Enhanced Network Redundancy Elimination for Connected Cars

    Masahiro YOSHIDA  Koya MORI  Tomohiro INOUE  Hiroyuki TANAKA  

     
    PAPER

      Pubricized:
    2022/05/27
      Vol:
    E105-B No:11
      Page(s):
    1372-1379

    Connected cars generate a huge amount of Internet of Things (IoT) sensor information called Controller Area Network (CAN) data. Recently, there is growing interest in collecting CAN data from connected cars in a cloud system to enable life-critical use cases such as safe driving support. Although each CAN data packet is very small, a connected car generates thousands of CAN data packets per second. Therefore, real-time CAN data collection from connected cars in a cloud system is one of the most challenging problems in the current IoT. In this paper, we propose an Edge computing-enhanced network Redundancy Elimination service (EdgeRE) for CAN data collection. In developing EdgeRE, we designed a CAN data compression architecture that combines in-vehicle computers, edge datacenters and a public cloud system. EdgeRE includes the idea of hierarchical data compression and dynamic data buffering at edge datacenters for real-time CAN data collection. Across a wide range of field tests with connected cars and an edge computing testbed, we show that the EdgeRE reduces bandwidth usage by 88% and the number of packets by 99%.

  • Deep Inspection of Unreachable BitTorrent Swarms

    Masahiro YOSHIDA  Akihiro NAKAO  

     
    PAPER

      Vol:
    E96-D No:2
      Page(s):
    249-258

    BitTorrent is one of the most popular P2P file sharing applications worldwide. Each BitTorrent network is called a swarm, and millions of peers may join multiple swarms. However, there are many unreachable peers (NATed (network address translated), firewalled, or inactive at the time of measurement) in each swarm; hence, existing techniques can only measure a part of all the peers in a swarm. In this paper, we propose an improved measurement method for BitTorrent swarms that include many unreachable peers. In essence, NATed peers and those behind firewalls are found by allowing them to connect to our crawlers by actively advertising our crawlers' addresses. Evaluation results show that the proposed method increases the number of unique contacted peers by 112% compared to the conventional method. Moreover, the proposed method increases the total volume of downloaded pieces by 66%. We investigate the sampling bias among the proposed and conventional methods, and we find that different measurement methods yield significantly different results.

  • A Protocol for Real-Time Remote Musical Session

    Masahiro YOSHIDA  Yuka OBU  Tatsuhiro YONEKURA  

     
    PAPER

      Vol:
    E88-D No:5
      Page(s):
    919-925

    Performing a musical session via networks requires real-time interaction. There exists, however, the problem of delay between the network nodes, which causes musical sessions become an impediment. To overcome this problem, we have proposed a new protocol for musical session called Mutual Anticipated Session (M.A.S.), which is a type of ensemble that controls appropriate timing of sounds. In the M.A.S, one player's performance precedes the other players', thus this performance is called a "precedent musical performance," and we call a time lapse between the players' performance as "precedent time." In the current M.A.S, it is assumed that the tempo during the performance is constant. In such a case, however, players' requirements to perform more expressively or more emotionally by varying the tempo are sacrificed. Thus, in this paper, enhancement of function that accommodates changes of the tempo by predicting tendency of it is realized. Finally we evaluate the enhancement both by system performance test and by task performance of subject experiments.

  • High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM

    Hitoshi MIWA  Shoji WADA  Yuji YOKOYAMA  Masayuki NAKAMURA  Tatsuyuki OHTA  Toshio MAEDA  Masahiro YOSHIDA  Hideuki MIYAZAWA  Noboru AKIYAMA  Kazuyuki MIYAZAWA  Jun MURATA  

     
    PAPER

      Vol:
    E75-C No:11
      Page(s):
    1344-1350

    This 0.8 µm 4 Mbit BiCMOS DRAM achieves the world's fastest chip-enable access time of 17 ns. BiCMOS technology has been employed because of its ability to enhance DRAM performance. Some new circuits, such as a dynamic pull-down type address buffer, a noise immune cascode amplifier, and an offset-cross output circuit are introduced to reduce access time. This paper explains in more detail the noise immune cascode amplifier, and the offset-cross output circuit. A conventional cascode amplifier can operate very rapidly in spite of a heavy parasitic capacitance associated with the data read out line of the memory array. However, when noise, which is inevitably caused by operation, appears on the power supply, bipolar transistors in cascode amplifier cut off, and the cascode amplifier loses its speed advantage. In the noise immune cascode amplifier, a resistor and two capaciters are added to maitain a stable base level of the bipolar transistors. So the cascode amplifier can continue to operate normally, despite the power supply noise. A conventional output circuit is composed of two level converters, four inverters and output transistors. The input swing (the level gap between the data level and the refernce level which are input to the level converters) is 0.5 V, which is not sufficient for the level converter to drive the load capacitance connected with the output transistors. To increase the drivability of the level converter, two 2-stage inverters must be inserted between the level converters and output transistors. In the proposed offset-cross circuit however, the input swing is increased to 1.5 V, which is sufficient for the level converter to drive the load capacitance directly, so the four inverters can be eliminated. The access time is improved by 1.5 ns using the noise immune cascode amplifier, and by 1.7 ns using the offset-cross output circuit. This chip is constructed using a conventional 0.8 µm BiCMOS process. Therefore, it can be used to realize a high speed and low cost memory system.