The Bach compiler is a behavioral synthesis tool, which synthesizes RT-level circuits from behavioral descriptions written in the Bach C language. It shortens the design period of LSI and helps designers concentrate on algorithm design and refinement. In this paper, we propose methods for optimizing the area and performance of algorithms described in Bach C. In our experiments, we optimized a Viterbi decoder algorithm using our proposed methods and synthesized the circuit using the Bach compiler. The conclusion is that the circuit produced using Bach is both smaller and faster than the hand-coded register transfer level (RTL) design. This proves that the Bach compiler produces high-quality results and the Bach C language is effective for describing the behavior of hardware at a high-level.

A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper first investigates such a complex scheduling mechanism, and formulates an optimal scheduling problem as a 0-1 integer programming problem such that given a prescribed number of control steps, the total cost of functional units can be minimized. In this formulation, each constraint is expressed in the form of a Boolean function, which is set equal to 1 or 0 according as the constraint is satisfied or not, respectively, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results are also shown, which demonstrate that our approach is of more practical use than the existing methods.

In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.

In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.

This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

This paper presents a new binding algorithm for a retargetable compiler which can deal with diverse architectures of application specific embedded processors. The architectural diversity includes a "non-orthogonal" datapath configuration where all the registers are not equally accessible by all the functional units. Under this assumption, binding becomes a hard task because inadvertent assignment of an operation to a functional unit may rule out possible assignment of other operations due to unreachability among datapath resources. We propose a new BDD-based algorithm to solve this problem. While most of the conventional methods are based on the covering of expression trees obtained by decomposing DFGs, our algorithm works directly on the DFGs so as to avoid infeasible bindings. In the experiments, a feasible binding which satisfies the reachability is found or the deficiency of datapath is detected within a few seconds.

This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.

This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.

An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.

In the floorplan design problem, soft blocks can take various rectilinear shapes. The conventional floorplanning methods, however, restrict their shapes only to rectangle. As a result, waste area often remains in the layout. Some floorplanning methods have been developed to handle rectilinear hard blocks, however, no floorplanning methods have been developed to optimize rectilinear soft blocks. In this paper, we propose a floorplanning method which places rectilinear soft blocks. The advantages of the method are reducing both waste area and wire length. We present Separate-Rejoin method which efficiently forms rectilinear shapes for soft blocks. The result is obtained quickly because the method is based on the slicing structure in spite of handling rectilinear block. Thus, our method is suitable for practical use in terms of layout area, wire length and processing time. We applied our method to a benchmark example and an industrial data. For the benchmark example, our method reduces waste area by 25% and wire length by 13% in comparison with the conventional rectangular soft block approach.