In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.

In the floorplan design problem, soft blocks can take various rectilinear shapes. The conventional floorplanning methods, however, restrict their shapes only to rectangle. As a result, waste area often remains in the layout. Some floorplanning methods have been developed to handle rectilinear hard blocks, however, no floorplanning methods have been developed to optimize rectilinear soft blocks. In this paper, we propose a floorplanning method which places rectilinear soft blocks. The advantages of the method are reducing both waste area and wire length. We present Separate-Rejoin method which efficiently forms rectilinear shapes for soft blocks. The result is obtained quickly because the method is based on the slicing structure in spite of handling rectilinear block. Thus, our method is suitable for practical use in terms of layout area, wire length and processing time. We applied our method to a benchmark example and an industrial data. For the benchmark example, our method reduces waste area by 25% and wire length by 13% in comparison with the conventional rectangular soft block approach.