IEICE TRANSACTIONS on Fundamentals
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Summary :
This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.
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- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1853-1860
- Publication Date
- 1997/10/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Masayuki YAMAGUCHI, Akihisa YAMADA, Toshihiro NAKAOKA, Takashi KAMBE, Nagisa ISHIURA, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1853-1860, October 1997, doi: .
Abstract: This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1853/_p
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@ARTICLE{e80-a_10_1853,
author={Masayuki YAMAGUCHI, Akihisa YAMADA, Toshihiro NAKAOKA, Takashi KAMBE, Nagisa ISHIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture Evaluation Based on the Datapath Structure and Parallel Constraint},
year={1997},
volume={E80-A},
number={10},
pages={1853-1860},
abstract={This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1853
EP - 1860
AU - Masayuki YAMAGUCHI
AU - Akihisa YAMADA
AU - Toshihiro NAKAOKA
AU - Takashi KAMBE
AU - Nagisa ISHIURA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.
ER -
English
