An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.

A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. In terms of the digital video transmission, the required performance of a multiplier is to operate at the speed of 20-100 MHz but with the precision of 8-10 bits. In the case of implementing such an FIR filter with more than a certain number of taps, the same number of multipliers are necessary to realize the speed. Moreover, even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier and FIR filter architecture is described, which is to be synthesized with the use of a high level synthesis tool of COMPASS Design Navigator, partly with the aid of the manual design by means of a 0.8µm CMOS library.

Since a human object is an important element of the moving pictures being processed by mobile terminals, establishing a human object extraction method encourages dissemination of new applications. In accordance with the requirement of mobile applications, this paper proposes a low-cost human object extraction method, which consists of a face object and a hair object extraction based on their color information and a simple body extraction utilizing the position information of the face object. In the proposed method, skin color and hair color are estimated through color space segmentation, and a human object is effectively extracted by using a radial active contour model. Simulation results of the human object extraction with the use of XScale processor claims that QCIF 15 fps video sequences can be processed in real time.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

Let G be a directed graph containing n nodes and m edges, with each edge of nonnegative length. Given two specified nodes s and t, the length of a k-tuple of edge-disjoint paths from s to t in G is the sum of the lengths of all the edges on these k paths. A polynomial time algorithm for finding a shortest k-tuple of edge-disjoint paths from s to t in G has been devised. Based on this algorithm, this paper considers the problem of finding a second shortest k-tuple of edge-disjoint paths from s to t in G, for which an O (min[n3, nm log n])-time is described.

A VLSI architecture of a motion estimator is described dedicatedly for the H. 263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional PE (Processing Element) array is devised to be tuned to the H. 263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1. 55 mm2 by using 0. 35 µm CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.

Two schemes are described for digital fault simulation; one is on MOS circuit modeling for detecting transistor stuck faults in bidirectional transfer gates, and the other is on fault collapsing for reducing the number of faults in gate level circuits which include transformed logic gates. By using the proposed technique, all stuck-at faults on signal lines and all transistor faults in MOS transmission gates can be modeled by the conventional stuck-at faults. Several experimental results are also shown to reveal that the proposed schemes can be effectively applied to fault simulation of VLSI circuits including bidirectional MOS transmission gates.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.11.4 mm2 in a 90 nm CMOS technology.

A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm2 with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

A new flow algorithm is described on the basis of the primal-dual method, which is to be adopted dedicatedly for the regeneration of optimal layouts for functional cells of the standard-cell level. In advance of discussing this main theme, the present paper first outlines a practical scheme of reusing those layouts which have been once generated for functional cells in an old fabrication technology, and then formulates an optimization problem for regenerating optimal layouts of functional cells under the constraints incurred by the renewal of design rules. An efficient algorithm proposed here aims at solving this optimization problem with the use of solution concepts for the minimum cost flow problem. A part of experimental results is also shown, which indicates that the proposed altorithm is the fastest for this optimization problem.

In a probabilistic graph (network), source-to-all-terminal (SAT) reliability may be defined as the probability that there exists at least one path consisting only of successful arcs from source vertex s to every other vertex. In this paper, we define an optimal SAT reliability formula to be the one with minimal number of literals or operators. At first, this paper describes an arc-reductions (open- or short-circuiting) method for obtaining a factored formula of directed graph. Next, we discuss a simple strategy to get an optimal formula being a product of the reliability formulas of vertex-section graphs, each of which contains a distinct strongly connected component of the given graph. This method reduces the computing cost and data processing effort required tu generate the optimal factored formula, which contains no identical product terms.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

In recent years, information devices with network communication ability have become very popular, and many people actually own such kind of devices. Those information devices, however, do not share users' data in spite of their communication ability. This paper proposes "OCEAN: Object Communication Environment for Arbitrary Network" architecture, which provides liaison of objects stored in each device according to their profiles and situations. It eliminates redundant user operation on information devices, and enables novel communication scheme among users by sharing common objects in those devices. Furthermore, it maximizes the effective use of each device's limitation according to each environment. Finally, in this paper, we discuss our prototype of OCEAN.

VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.

This paper describes a new approach to the digital watermarking of motion pictures dedicatedly for the MPEG-4 video coding, which intends to enhance the error detection ability. The conventional method lacks not only the detection ability but also the compatibility with video decoders widely used today. Thus in this approach the digital watermarks are to be embedded into the quantized DCT (Discrete Cosine Transform) coefficients for the error detection, where the prevention of the picture quality degradation is also attempted. Experimental results are shown to demonstrate that the error detection ability of the proposed approach is significantly improved, as compared with that of the conventional method, and that the degradation of the picture quality by the watermarking is extremely small.

A new error correction block based Hybrid ARQ protocol, in which PHY layer packets are composed of multiple error correction blocks, is devised together with a retransmission control scheme constructed on the basis of these error correction blocks. This protocol is designed dedicatedly for mobile AV stations to provide the high quality digital video transmission through a radio channel. To analyze the performance of this protocol, the frame loss rate vs. the uncorrectable error probability is simulated, in comparison with the ordinary packet based retransmission control. A wireless video transmission system using IEEE802.11b PHY is also described, which has been developed with the use of a Medium Access Control (MAC) LSI to perform the proposed protocol.

A single chip motion estimator is described dedicatedly for MPEG2 MP＠HL moving pictures. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. A novel mechanism is introduced into the full-search procedure, which attempts the maximum possible reuse of reference pixels in order to reduce the bandwidth of the frame memory interface. The proposed motion estimator is integrated in a 0.6 µm triple-metal CMOS chip, which contains 1,450 K transistors on a 12.713.7 mm2 die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP＠HL.

This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.