This paper proposes an LDMOSFET (Lateral Double-diffused MOSFET) that has the robustness against the hardest ESD (Electrostatic Discharge) requirement for automobile ECUs (Electronic Control Units) of discharging 25 kV 150 pF through 150 ohm 1 µH without external protecting circuits. The basic idea to achieve this is to add a novel discharge circuit to an LDMOSFET, which turns on when Human Body Model (HBM) type ESD is applied, and to consume the discharge energy in SOA (Safe Operating Area) in the LDMOSFET, avoiding localized current crowding of a parasitic bipolar transistor which causes the conventional ESD device failure. First, dynamics of current crowding when a grounded gate LDMOSFET is exposed to ESD stress is described by means of a circuit level SPICE simulation on a parallel distributed device model. Then a novel ESD turn-on LDMOSFET with a discharge MOSFET is proposed, which has ESD robustness of 25 kV. Finally the ESD measurements of the new device are shown to be in good accordance with estimation and to satisfy the target.

With the fully depleted ultra-thin-film SOI CMOS, one important issue is controlling the threshold voltage (Vth) while maintaining high speed operation and low power consumption. To control the Vth, applying a bias voltage to the substrate is one of the most practical methods. We suggest a fully depleted ultra-thin-film SOI CMOS with a floating back gate, which is formed at the lower part of the channel field inside the substrate and stores electrons injected into it. This device can eliminate the necessity of an extra circuit or a separate power supply to apply a negative voltage. The silicon wafer direct bonding technique is used to construct this device. With the prototyped devices, we can successfully control the Vth for both the nMOSFET and pMOSFET at around 0.5 V by controlling the quantity of the electric charges injected into the floating back gate.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

This paper presents various Iterative Progressive Numerical Methods (IPNMs) for the computation of electromagnetic (EM) wave scattering from many objects. We previously modified the original IPNM from the standpoint of the classical and the IDR-based linear iterative solvers. We demonstrate the performance of the IDR(s)-based IPNMs through some numerical examples of EM wave scattering from regularly placed 27 perfectly electric conducting spheres.

This paper presents the iterative progressive numerical methods (IPNMs) based on the induced dimension reduction (IDR) theorem. The IDR theorem is mainly utilized for the development of new nonstationary linear iterative solvers. On the other hand, the use of the IDR theorem enables to revise the classical linear iterative solvers like the Jacobi, the Gauss-Seidel (GS), the relaxed Jacobi, the successive overrelaxation (SOR), and the symmetric SOR (SSOR) methods. The new IPNMs are based on the revised solvers because the original one is similar to the Jacobi method. In the new IPNMs, namely the IDR-based IPNMs, we repeatedly solve linear systems of equations by using a nonstationary linear iterative solver. An initial guess and a stopping criterion are discussed in order to realize a fast computation. We treat electromagnetic wave scattering from 27 perfectly electric conducting spheres and reports comparatively the performance of the IDR-based IPNMs. However, the IDR-based SOR- and the IDR-based SSOR-type IPNMs are not subject to the above numerical test in this paper because of the problem with an optimal relaxation parameter. The performance evaluation reveals that the IDR-based IPNMs are better than the conventional ones in terms of the net computation time and the application range for the distance between objects. The IDR-based GS-type IPNM is the best among the conventional and the IDR-based IPNMs and converges 5 times faster than a standard computation by way of the boundary element method.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.

We describe the implementation of an iterative method with the goal of gaining a long vector length. The strategy for vectorization by means of multipoint stencils used for discretization of the partial differential equations is discussed. Numerical experiments show that the strategy that requires certain restrictions on the number of grid points in the x and y directions improves the performance on the vector supercomputer.