The majority of independent locomotion microrobots pack batteries as their energy source. However, because the energy that can be stored in a battery is proportional to its volume, the operating time becomes shorter as the robot becomes smaller. To solve this problem the energy must be supplied from outside by wireless transmission. We propose a microwave energy transmission system for microrobots in metal piping. Because microwave is rectified and converted in the form of electric energy in this system, we developed a receiving antenna for microrobots in piping and a microwave rectifying circuit to generate high voltage. These were loaded on a microrobot, tested to drive a locomotive mechanism, and the efficiency of the proposed system was confirmed.

The development of highly accurate and durable control system is becoming a must for todays high performance automobiles. For example, it is necessary to up-grade todays materials and methods creating more sensitive sensors, higher speed processors and more accurate actuators, while also being more durable. Thus, the development of a CMOS time-to-digital converter LSI with half-nanosecond resolution, which controls only pulse signals was achieved by employing 1.5 µm CMOS technology. The new signal detecting circuit, 1.1 mm2 in size, converts time to numerical values over a wide measurement range (13 bits). The compact digital circuit employs a newly developed "ring gate delay system". Within the LSI the fully digital circuit is highly durable. This allows it to be utilized even under severe conditions (for example an operating ambient temperature of 130). In order to measure time accurately, a method of correcting the variation of measurement time data employing a real-time conversion fully digital circuit is described. This method allows for fully automatic correction with a microcomputer, so no manual adjustment is required. In addition to sensor circuit applications, the LSI has great potential for Application Specific Integrated Circuit, (ASIC) such as a function cell with is a completely new method of measuring time.

With the fully depleted ultra-thin-film SOI CMOS, one important issue is controlling the threshold voltage (Vth) while maintaining high speed operation and low power consumption. To control the Vth, applying a bias voltage to the substrate is one of the most practical methods. We suggest a fully depleted ultra-thin-film SOI CMOS with a floating back gate, which is formed at the lower part of the channel field inside the substrate and stores electrons injected into it. This device can eliminate the necessity of an extra circuit or a separate power supply to apply a negative voltage. The silicon wafer direct bonding technique is used to construct this device. With the prototyped devices, we can successfully control the Vth for both the nMOSFET and pMOSFET at around 0.5 V by controlling the quantity of the electric charges injected into the floating back gate.

A 3-dimensional specific thickness profile was fabricated on a thin glass diaphragm lens to reduce aberration at short focal distances for greater dynamic focusing. The deformation of the diaphragm was calculated by stress analysis utilizing the Finite Element Method (FEM). Geometric non linearity is considered in the FEM analysis. The glass diaphragm is 10 mm in diameter and the average thickness is 11 µm. To obtain both a curved shape and an optical surface on the glass diaphragm, the 3-dimensional precision grinding technique was utilized. The processed shape matches the designed one with less than 0.3 µm deviation, and the average surface roughness is 0.005 µm. Optical characteristics of the dynamic focusing lens having a specific thickness profile, were measured by Modulation Transfer Function (MTF) measurement equipment. At a focal distance of 250 mm, the specific thickness diaphragm lens resolution is 10 cycles/mm, whereas, the uniform thickness diaphragm is 4 cycles/mm. Even at other focal distances, the specific thickness diaphragm shows superior optical characteristics in comparison with those of the uniform thickness diaphragm. The 3-dimensional profile diaphragm resolution is 2.5 times finer at a focal distance of 250 mm, thus, being capable of displacement control for variable optic devices. This was achieved by employing semiconductor processing methods in conjunction with precision grinding techniques which are necessary for fabricating micro structures.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.