IEICE TRANSACTIONS on Electronics
Phenomenon and Mechanism of CMOS Latch-up Induced by Substrate Voltage Fluctuation in Thick Film SOI Structure
Summary :
The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.12 pp.1447-1452
- Publication Date
- 1992/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
- Category
- SOI Devices
Authors
Keyword
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Hitoshi YAMAGUCHI, Hiroaki HIMI, Seiji FUJINO, Tadashi HATTORI, "Phenomenon and Mechanism of CMOS Latch-up Induced by Substrate Voltage Fluctuation in Thick Film SOI Structure" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 12, pp. 1447-1452, December 1992, doi: .
Abstract: The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_12_1447/_p
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@ARTICLE{e75-c_12_1447,
author={Hitoshi YAMAGUCHI, Hiroaki HIMI, Seiji FUJINO, Tadashi HATTORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Phenomenon and Mechanism of CMOS Latch-up Induced by Substrate Voltage Fluctuation in Thick Film SOI Structure},
year={1992},
volume={E75-C},
number={12},
pages={1447-1452},
abstract={The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Phenomenon and Mechanism of CMOS Latch-up Induced by Substrate Voltage Fluctuation in Thick Film SOI Structure
T2 - IEICE TRANSACTIONS on Electronics
SP - 1447
EP - 1452
AU - Hitoshi YAMAGUCHI
AU - Hiroaki HIMI
AU - Seiji FUJINO
AU - Tadashi HATTORI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1992
AB - The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.
ER -
English
