The threading dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been invenstigated using Secco etching, cross-sectional transmission electron microscopy and Raman spectroscopy. The breakdown voltage of the buried oxide layer has also been studied. The dislocation density is greatly affected by the dose and the wafer temperature during implantation. The SIMOX wafer implanted at 180 keV with a substoichiometric dose of 0.4 10¹⁸ O⁺ cm^-2 at 550 and subsequently annealed at 1350 has an extremely low dislocation density on the order of 10² cm^-2. The effect of the wafer temperature on the reduction of the dislocation density is discussed.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 10¹¹/cm² negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

The interface between laser-recrystallized Si and SiO₂ is investigated by means of capacitance-voltage curve measurements. The recrystallization is performed by scanning cw Ar⁺ laser. The change in the C-V curves shows that the laser-recrystallization generates positive charge and the fast interface states at the Si-SiO₂ interface, and creates n-type defects in recrystallized bulk silicon. Nominal interface charge increases linearly with a laser power. The increase in the charge is enhanced by fast laser-beam scanning velocity. The change in the C-V curve is suppressed, if a substrate is heated up to 450 during recrystallization. Complete recovery of the induced change in the C-V curves requires a subsequent furnace annealing at a temperature as high as 1100. These phenomena are explained by the generation of oxygen vacancy at the Si-SiO₂ interface and quenched-in point defects in the recrystallized Si. The oxygen vacancy is produced by a reaction between the melted Si and SiO₂. The quenched-in defects are produced during fast cooling of the melted Si.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO₂ is very low. If there are voids in the SiO₂ layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

This paper describes high-temperature operation of nMOSFET on bonded SOI. A long-channel nMOSFET is fabricated on bonded SOI (Si layer thickness 0.3 µm), SOS (Si layer thickness 0.3 µm), and bulk Si, Bonded SOI is produced using pulse-field-assisited bonding and resistivity-sensitive etching. The high-temperature operation of bonded SOI nMOSFET is demonstrated and compared with SOS and bulk MOSFETs. The leakage current variation with temperature is signnificantly smaller in bonded SOI and in SOS than in bulk MOSFETs. At high temperatures, the drain current to leakage current ratio is 100 times higher in bonded SOI than in SOS and bulk devices. At 300, a ratio of 10⁴ is obtained for the bonded SOI nMOSFET. The ratio is expected to be even higher if a reduced channel length and ultrathin (less than 0.1 µm) bonded SOI is used.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N^- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N^- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.

Hot-carrier characteristics in ultra-thin SOI MOSFET's (T-SOI MOSFET's) with gate-overlapped LDD have been investigated. The change in transistor static characteristics after hot carrier stress was mainly observed as positive threshold voltage (V_t) shifts due to trapped electrons, while in bulk-Si MOSFET's drain current degradation was dominant. The hot-carrier life time in T-SOI MOSFET's was comparable to that in bulk-Si devices at low drain voltage, but the life time dependence on drain voltage was different from that in bulk-Si MOSFET's, and the V_t degraded rapidly at the condition that parasitic bipolar breakdown began to occur. This implies that the drain supply voltage in T-SOI MOSFET's is determined directly by parasitic bipolar breakdown voltage unlike bulk-Si MOSFET's in which it is determined by hot-carrier reliability. The gate-overlapped LDD structure was compared with single drain structure and proved to provide better hot-carrier endurance by the improvement of the parasitic bipolar breakdown voltage. The hot-carrier reliability in the back channels of T-SOI MOSFET's was also investigated, and it was found that the back channel tends to be degraded more easily than front channel with large positive V_t shifts. These results suggest that the front V_t shifts in T-SOI devices are related with electron injection into the back surface of the T-SOI layer through charge coupling at the condition that the parasitic bipolar breakdown occurs.

A study of hot-carrier-induced photon emission in thin SOI/MOSFETs has been carried out both for bonded-SOI and SIMOX/SOI. The photon emission is observed not only in the drain region but also in the source region for SOI/MOSFETs, whereas only in the drain region for conventional bulk MOSFETs. From the emission spectrum, it can be concluded that the emission mechanism of the source region is probably a photon-assisted direct recombination of electrons and holes, while both the recombination and Bremsstrahlung are the possible mechanism for the drain region. The total photo intensity from SOI/MOSFETs increases as the SOI film thickness decreases, showing that strong impact ionization occurs near the drain region for thinner SOI devices. The relation between the lifetime and the photo intensity for SOI/MOSFETs is very similar to that between the lifetime and the substrate current for conventional bulk/MOSFETs, proving that photon emission is a good indicator of the hot carrier degradation in thin SOI/MOSFETs. The lifetime measurement using the photon emission both for SOI and bulk devices indicates that longer lifetime can be expected for thin film SOI/MOSFETs with a reduced drain bias which will be indispensable for future sub-half micron MOSFETs.

The velocity overshoot and hot carrier effects in thin-film SOI-nMOSFETs have been studied using a two-dimensional device simulator based on the energy transport model. It has been found that the velocity overshoot effect in a nearly-intrinsic device becomes pronounced in the short channel region because of their high carrier mobility. The distribution of the electron velocity in a 0.2 µm channel length SOI device shows that the velocity overshoot takes place over the whole channel region, which enhances the drive capability significantly. The behaviors of hot carriers injected into the gate oxide and the back oxide have been simulated for the first time by using the energy distribution functions of electrons and holes at the SOI-SiO₂ interface and solving the current continuity equation in the oxide layer. It has been found that hot carriers are injected not only into the gate oxide but also into the back oxide, which can degrade hot-carrier reliability in small-featured thin-film SOI-MOSFETs.

Hot carrier stressing is carried out on ultra-thin-film SOI/pMOSFET's under a front gate operation. Degradations of both front and back gate characteristics are estimated. Effects of trapped electron in the front and the back gate oxide on device characteristics are also estimated. In a triode region, it is found that degradation in front gate characteristics is correlated with that in back gate characteristics, although ΔV_th(b) is twenty times as large as ΔV_th(f), due to difference between the front gate and the buried oxide thickness. In a pentode region, Δβ/β₀ in a forward-mode is larger than that in a reverse-mode. This is because of the non-uniformly distributed hot carrier damage along the channel. Based on the charge-coupling theory, damages in the front gate and buried oxide by hot carrier effects are estimated separately. Flat-band-voltage shift in the back gate due to trapped charges in the buried oxide, is obtained from V_th (f) dependence on back gate bias. For L_eff=2.0 µm devices, the flat-band-voltage shift varies in the range of 1.00 to 1.50 V. This indicates that trapped electrons are created in the buried oxide. Trapped electrons in the buried oxide increase g_m(f) through the effect equivalent to back gate bias. From g_m(f) dependence on back gate bias, it is found that effective channel length is decreased by trapped electrons in the front gate oxide near the drain. Therefore, it is worth noticing that, in hot carrier effects in ultra-thin-film SOI/pMOSFET's, g_m is increased not only by the reduction of effective channel length but also by the equivalent back gate bias effect.

A 0.1-µm-gate CMOS/SIMOX has been successfully fabricated using high quality SIMOX substrates. The propagation delay time for the 0.1-µm-gate CMOS/SIMOX is not so noticeable due to the parasitic resistance of the source and drain regions. We anticipate 0.1-µm-gate CMOS/SIMOX devices with a delay time of less than 20 ps at a supply voltage of 1.5 V by reducing the remaining parasitic resistance and capacitances.

Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 10¹⁶ cm^-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.

Dynamic performance of ultra-thin SIMOX (Separation by IMplanted OXgen) CMOS circuits has been studied using ring oscillators. A novel concept of current-delay product, along with an equivalent linear resistance of MOSFETs, is applied for deriving effective load capacitance of near 0.1 µm gate CMOS circuits. Calculation results showed quatitative agreement with measurement data. It was found that the gate-fringing capacitance limits the delay time is the case of under 0.2 µm gate-length. The lower bound of power-delay product of SIMOX/SOI is expected as low as 0.2 fJ for the gate length of 0.15 µm at the supply voltage of 1.5 V.

We fabricated mixed-signal ICs (MSICs) using wafer-bonded SOI devices with a film several microns thick. We found the MOSFETs on wafer-bonded SOI had characteristics as good as those on a conventional wafer provided the active Si layer is more than 2 µm thick. We fabricated a 16-bit SOI-CMOS delta-sigma A/D converter that suppressed digital noise interference via the substrate. We also fabricated a rectifier-merged SOI-BiCMOS circuit. The resulting characteristics were good, and not possible using conventional junction isolation. Our results suggest that SOI-based isolation is a key technology in integrating devices and systems on a single chip.

SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.

A detailed numerical solution of the design criteria of in-phase lateral and single-longitudinal-mode operation GaInAsP/InP DFB laser arrays is presented. The analysis, including broad-area pumped and stripe-geometry pumped index-guided arrays, was carried out on the basis of the eigenvalue equation method. It is shown that there exists a cut-off array pitch _co, at which all of the higher-order array modes are cut off. For the pitch larger than the cut-off pitch _co, the modal discrimination is evaluated by the threshold gain difference between the in-phase lateral and higher-order array modes. As a result, the modal discrimination was found to decrease with the increase of the number of elements and the array pitch which is limited to be smaller than twice the cut-off pitch _co to attain a stable in-phase lateral- and single-longitudinal-mode operation.

Stability property of an optically injection-locked semiconductor laser taking account of gain saturation is discussed. Numerical analysis shows that stable locking region is broadened due to gain saturation. This is because of rapid damping of relaxation oscillation due to gain saturation. It is also found that stable locking region is also broadened with increasing injection current since damping of relaxation oscillation becomes strong with increasing injection current. Numerical calculations of lasing spectrum show that the magnitude of sidepeaks appeared at harmonics of relaxation oscillation frequency under unstable locking condition are suppressed due to gain saturation.

The static characteristics of GaInAs(P)/GaInAsP quantum well laser diodes (QW LDs), with graded-index separate-confinement-heterostructure (GRIN-SCH) grown by metalorganic chemical vapor deposition (MOCVD), have been investigated experimentally in terms of threshold current density, internal waveguide loss, differential quantum efficiency and light output power. Very low threshold current density of 410 A/cm², high characteristic temperature of 113 K, low internal waveguide loss of 5 cm^-1, high differential quantum efficiency of 82% and high light output power of 100 mW were obtained in 1.3 µm GRIN-SCH multiple quantum well (MQW) LDs by optimizing the quantum well structure including confinement layer and cavity design. Excellent uniformity for the threshold current, quantum efficiency and emission wavelength was obtained in all MOCVD grown buried heterostructure GRIN-SCH MQW LDs. Lasing characteristics of 1.5 µm GRIN-SCH MQW LDs are also described.