IEICE TRANSACTIONS on Electronics
Bonded SOI with Polish-Stopper Technology for ULSI
Summary :
SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.12 pp.1522-1528
- Publication Date
- 1992/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
- Category
- SOI LSIs
Authors
Yoshihiro MIYAZAWA
Makoto HASHIMOTO
Naoki NAGASHIMA
Hiroshi SATO
Muneharu SHIMANOE
Katsunori SENO
Fumio MIYAJI
Takeshi MATSUSHITA
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yoshihiro MIYAZAWA, Makoto HASHIMOTO, Naoki NAGASHIMA, Hiroshi SATO, Muneharu SHIMANOE, Katsunori SENO, Fumio MIYAJI, Takeshi MATSUSHITA, "Bonded SOI with Polish-Stopper Technology for ULSI" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 12, pp. 1522-1528, December 1992, doi: .
Abstract: SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_12_1522/_p
Copy
@ARTICLE{e75-c_12_1522,
author={Yoshihiro MIYAZAWA, Makoto HASHIMOTO, Naoki NAGASHIMA, Hiroshi SATO, Muneharu SHIMANOE, Katsunori SENO, Fumio MIYAJI, Takeshi MATSUSHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Bonded SOI with Polish-Stopper Technology for ULSI},
year={1992},
volume={E75-C},
number={12},
pages={1522-1528},
abstract={SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Bonded SOI with Polish-Stopper Technology for ULSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 1522
EP - 1528
AU - Yoshihiro MIYAZAWA
AU - Makoto HASHIMOTO
AU - Naoki NAGASHIMA
AU - Hiroshi SATO
AU - Muneharu SHIMANOE
AU - Katsunori SENO
AU - Fumio MIYAJI
AU - Takeshi MATSUSHITA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1992
AB - SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.
ER -
English
