This paper describes the use of direct wafer bonding technique to implement the novel concept of "free-material and free-orientation integration" which we propose. The technique is applied for various wafer combinations of an In-Ga-As-P material system with lattice- and orientation-mismatches. The properties of the bonded structures are studied in terms of the crystalline and electrical characterization. The high crystalline quality of the bonded structures with those mismatches is proved by transmission electron microscopy, and good electrical conduction was attained in some bonded structures of InP and GaAs. (001) InP-based 1.55-µm wavelength lasers are fabricated on (110) GaAs substrate by direct wafer bonding. The light-current characteristics of the lasers are almost identical to those of lasers fabricated on (001) InP and (001) GaAs substrates, while the turn-on voltage is a little bit higher due to the higher barrier height at the bonded interface. The practicability in those lasers are also examined. Furthermore, we show direct wafer bonding of a (001) InP-based structure and a (110) Si substrate with a GaAs buffer layer, aligning the cleavage planes of the InP and the Si. The results demonstrate the remarkable feasibility of using the direct wafer bonding technique to obtain integrated structures of material- and orientation-mismatched wafers with satisfactory quality.

The advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart-Cut(R) SOI process used for the manufacture of the Unibond(R) SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart-Cut(R) process is described in detail and material characteristics of Unibond(R) wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO2 to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO2 using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.

SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

In this study, we evaluate the electrical characteristics of the SOI layer made by the wafer bonding method using a laser/microwave method. We use a He-Ne laser pulse for the photoconductivity modulation method and a semiconductor laser diode for the photoconductivity decay method as the carrier injection light source. The detected signal intensity at the void area decreases as compared with that at the center area of the SOI layer where there are no voids. The positions of the voids revealed by the proposed method are in good agreement with those by X-ray topography. We also measure the lifetime by the photoconductivity decay method using a laser diode. The lifetime at the void area is much shorter than that at the center area. It is considered that the decrease in the detected signal intensity at the void area is due to reduction in the minority carrier lifetime.