We have developed a practical 3-D integrated process simulator (3-D MIPS) based on the orthogonal grid. 3-D MIPS has a 3-D topography simulator (3-D MULSS) and 3-D impurity simulator which simulates the processes of ion implantation, impurity diffusion and oxidation. In particular, its diffusion and segregation model is new and practical. It assumes the continuity of impurity concentration at the material boundary in order to coordinate with the topography simulator (3-D MULSS) with cells in which two or more kinds of materials exist. And then, we introduced a time-step control method using the Dufort-Frankel method of diffusion analysis for stable calculation, and a selective oxidation model to apply to more general structures than LOCOS structure. After that, the 3-D MIPS diffusion model is evaluated compared with experimental data. Finally, the 3-D MIPS is applied to 3-D simulations of the nMOS Tr. structure with LOCOS isolation, wiring interconnect and pn-junction capacitances, and DRAM storage node area.

A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).

Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 1016 cm-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.

This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

It is still an open problem to elucidate the scaling merits of an embedded SRAM with Low Operating Power (LOP) MOSFETs fabricated in 50, 70 and 100 nm CMOS technology nodes. Taking into account a realistic SRAM cell layout, we evaluated the parasitic capacitance of the bit line (BL) as well as the word line (WL) in each generation. By means of a 3-Dimensional (3D) interconnect simulator (Raphael), we focused on the scaling merit through a comparison of the simulated SRAM BL delay for each CMOS technology node. In this paper, we propose two kinds of original interconnect structure which modify ITRS (International Technology Roadmap for Semiconductors), and make it clear that the original interconnect structures with reduced gate overlap capacitance guarantee the scaling merits of SRAM cells fabricated with LOP MOSFETs in 50 and 70 nm CMOS technology nodes.

A design methodology optimizing constant-charge-injection programming (CCIP) for assist-gate (AG)-AND flash memories is proposed. Transient circuit simulations using an array-level model including lucky electron model (LEM) current source describing hot electron physics enables a concept design over the whole memory-string in advance of wafer manufacturing. The dynamic programming behaviors of various CCIP sequences, obtained by circuit simulations using the model is verified with the measurement results of 90-nm AG-AND flash memory, and we confirmed that the simulation results sufficiently agree with the measurement, considering the simulation results give optimum bias AG voltage approximately within 0.2 V error. Then, we have applied the model to a conceptual design and have obtained optimum bit line capacitance value and CCIP sequence those are the most important issues involved in high-throughput programming for an AG-AND array.

A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 1019 cm-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.