IEICE TRANSACTIONS on Electronics
Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits
Summary :
A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.8 pp.1317-1323
- Publication Date
- 2000/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
- Category
- Circuit Applications
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Keyword
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Ken-ichiro SONODA, Motoaki TANIZAWA, Kiyoshi ISHIKAWA, Norihiko KOTANI, Tadashi NISHIMURA, "Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 8, pp. 1317-1323, August 2000, doi: .
Abstract: A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_8_1317/_p
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@ARTICLE{e83-c_8_1317,
author={Ken-ichiro SONODA, Motoaki TANIZAWA, Kiyoshi ISHIKAWA, Norihiko KOTANI, Tadashi NISHIMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits},
year={2000},
volume={E83-C},
number={8},
pages={1317-1323},
abstract={A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1317
EP - 1323
AU - Ken-ichiro SONODA
AU - Motoaki TANIZAWA
AU - Kiyoshi ISHIKAWA
AU - Norihiko KOTANI
AU - Tadashi NISHIMURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2000
AB - A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).
ER -
English
